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參數(shù)資料
| 型號： | ST16C2550IQ48TR-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 4/37頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART FIFO 16B DUAL 48TQFP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 特點(diǎn)： | * |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 16 字節(jié) |
| 規(guī)程： | RS232，RS485 |
| 電源電壓： | 2.97 V ~ 5.5 V |
| 帶故障啟動位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
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ST16C2550
12
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 4.4.1
The C2550 divides the basic external clock by 16. The basic 16X clock provides table rates to support standard
and custom applications using the same system design. The Baud Rate Generator divides the input 16X clock
by any divisor from 1 to 216 -1. The rate table is configured via the DLL and DLM internal register functions.
Customized Baud Rates can be achieved by selecting the proper divisor values for the MSB and LSB sections
of baud rate generator.
Table 5 shows the standard data rates available with a 14.7456 MHz crystal or external clock at 16X sampling
rate. When using a non-standard frequency crystal or external clock, the divisor value can be calculated for
DLL/DLM with the following equation.
divisor (decimal) = (XTAL1 clock frequency) / (serial data rate x 16)
TABLE 5: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK
OUTPUT Data Rate
MCR Bit-7=0
DIVISOR FOR 16x
Clock (Decimal)
DIVISOR FOR 16x
Clock (HEX)
DLM PROGRAM
VALUE (HEX)
DLL PROGRAM
VALUE (HEX)
DATA RATE
ERROR (%)
400
2304
900
09
00
0
2400
384
180
01
80
0
4800
192
C0
00
C0
0
9600
96
60
00
60
0
19.2k
48
30
00
30
0
38.4k
24
18
00
18
0
76.8k
12
0C
00
0C
0
153.6k
6
06
00
06
0
230.4k
4
04
00
04
0
460.8k
2
02
00
02
0
921.6k
1
01
00
01
0
2.9
Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 16 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal
clock. A bit time is 16 clock periods. The transmitter sends the start-bit followed by the number of data bits,
inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are reported in
the Line Status Register (LSR bit-5 and bit-6).
2.9.1
Transmit Holding Register (THR) - Write Only
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 16 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
2.9.2
Transmitter Operation in non-FIFO Mode
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
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相關(guān)代理商/技術(shù)參數(shù) |
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| ST16C2552 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO |
| ST16C2552_06 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO |
| ST16C2552CJ | 制造商:EXAR 功能描述:IC , Dual UART 4MBPS 5.5 44 PLCC 制造商:Exar Corporation 功能描述: 制造商:XIC 功能描述: 制造商:Exar Corporation 功能描述:UART, 44 Pin, Plastic, PLCC |
| ST16C2552CJ-0A-EB | 功能描述:界面開發(fā)工具 Supports C2550 44 ld PLCC, ISA Interface RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| ST16C2552CJ44 | 制造商:Exar Corporation 功能描述: 制造商:Exar Corporation 功能描述:UART, 44 Pin, Plastic, PLCC 制造商:EXER 功能描述:UART, 44 Pin, Plastic, PLCC 制造商:STAR 功能描述:UART, 44 Pin, Plastic, PLCC 制造商:STARTECH 功能描述:UART, 44 Pin, Plastic, PLCC |
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