參數(shù)資料
型號(hào)： SSTUA32866EC,557
廠商： NXP SEMICONDUCTORS
元件分類： 鎖存器
英文描述： 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
封裝： 13.50 X 5.50 MM, 1.05 MM HEIGHT, PLASTIC, SOT-536-1, LFBGA-96
文件頁數(shù)： 3/28頁
文件大小： 153K
代理商： SSTUA32866EC,557
SSTUA32866_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 26 March 2007
11 of 28
NXP Semiconductors
SSTUA32866
1.8 V DDR2-667 congurable registered buffer with parity
10. Characteristics
Table 7.
Characteristics
At recommended operating conditions (see Table 6); unless otherwise specied.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOH
HIGH-level output voltage
IOH = 6 mA; VDD = 1.7 V
1.2
-
V
VOL
LOW-level output voltage
IOL = 6 mA; VDD = 1.7 V
-
0.5
V
II
input current
all inputs; VI =VDD or GND; VDD = 2.0 V
-
±5
A
IDD
supply current
static standby; RESET = GND;
IO = 0 mA; VDD = 2.0 V
--
2
mA
static operating; RESET = VDD;
IO = 0 mA; VDD = 2.0 V;
VI =VIH(AC) or VIL(AC)
-
40
mA
IDDD
dynamic operating current
per MHz
clock only; RESET = VDD;
VI =VIH(AC) or VIL(AC);
CK and CK switching at 50 % duty cycle.
IO = 0 mA; VDD = 1.8 V
-16
-
A
per each data input, 1 : 1 mode;
RESET = VDD; VI =VIH(AC) or VIL(AC);
CK and CK switching at 50 % duty cycle.
One data input switching at half clock
frequency, 50 % duty cycle. IO = 0 mA;
VDD = 1.8 V
-11
-
A
per each data input, 1 : 2 mode;
RESET = VDD; VI =VIH(AC) or VIL(AC);
CK and CK switching at 50 % duty cycle.
One data input switching at half clock
frequency, 50 % duty cycle. IO = 0 mA;
VDD = 1.8 V
-19
-
A
Ci
input capacitance
data and CSR inputs; VI =Vref ± 250 mV;
VDD = 1.8 V
2.5
-
3.5
pF
CK and CK inputs; VICR = 0.9 V;
Vi(p-p) = 600 mV; VDD = 1.8 V
2-
3pF
RESET input; VI =VDD or GND;
VDD = 1.8 V
3-
4pF
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參數(shù)描述
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SSTUA32S865ET 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-667 RDIMM applications
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