參數(shù)資料
型號： SSTUA32866EC,557
廠商： NXP SEMICONDUCTORS
元件分類： 鎖存器
英文描述： 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
封裝： 13.50 X 5.50 MM, 1.05 MM HEIGHT, PLASTIC, SOT-536-1, LFBGA-96
文件頁數(shù)： 28/28頁
文件大?。?/td> 153K
代理商： SSTUA32866EC,557
SSTUA32866_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 26 March 2007
9 of 28
NXP Semiconductors
SSTUA32866
1.8 V DDR2-667 congurable registered buffer with parity
7.1 Function table
[1]
Q0 is the previous state of the associated output.
[1]
PPO0 is the previous state of output PPO; QERR0 is the previous state of output QERR.
[2]
Data inputs = D2, D3, D5, D6, D8 to D25 when C0 = 0 and C1 = 0.
Data inputs = D2, D3, D5, D6, D8 to D14 when C0 = 0 and C1 = 1.
Data inputs = D1 to D6, D8 to D10, D12, D13 when C0 = 1 and C1 = 1.
[3]
PAR_IN arrives one clock cycle (C0 = 0), or two clock cycles (C0 = 1), after the data to which it applies.
[4]
This condition assumes QERR is HIGH at the crossing of CK going HIGH and CK going LOW. If QERR is LOW, it stays latched LOW for
two clock cycles or until RESET is driven LOW.
Table 3.
Function table (each ip-op)
L = LOW voltage level; H = HIGH voltage level; X = don’t care;
↑ = LOW-to-HIGH transition; ↓ = HIGH-to-LOW transition
Inputs
RESET
DCS
CSR
CK
Dn, DODTn,
DCKEn
Qn
QCS
QODT,
QCKE
HL
L
↑↓
LL
L
HL
L
↑↓
HH
L
H
L
L or H
X
Q0
HL
H
↑↓
LL
L
HL
H
↑↓
HH
L
H
L
H
L or H
X
Q0
HH
L
↑↓
LL
H
L
HH
L
↑↓
HH
H
L
L or H
X
Q0
HH
H
↑↓
LQ0
HL
HH
H
↑↓
HQ0
HH
H
L or H
X
Q0
L
X or oating
L
Table 4.
Parity and standby function table
L = LOW voltage level; H = HIGH voltage level; X = don’t care;
↑ = LOW-to-HIGH transition; ↓ = HIGH-to-LOW transition
Inputs
Outputs[1]
RESET
DCS
CSR
CK
∑ of inputs = H
(D1 to D25)
PAR_IN[2]
PPO[3]
QERR[4]
HL
X
↑↓
even
L
H
HL
X
↑↓
odd
L
H
L
HL
X
↑↓
even
H
L
HL
X
↑↓
odd
H
L
H
HH
L
↑↓
even
L
H
HH
L
↑↓
odd
L
H
L
HH
L
↑↓
even
H
L
HH
L
↑↓
odd
H
L
H
HH
H
↑↓
X
PPO0
QERR0
H
X
L or H
X
PPO0
QERR0
L
X or oating
L
H
相關PDF資料
PDF描述
SSTUA32866EC/G,551 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
SSTUA32866EC/G,557 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
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相關代理商/技術參數(shù)
參數(shù)描述
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SSTUA32S865ET 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-667 RDIMM applications
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