參數(shù)資料
型號： SSTUA32866EC,557
廠商： NXP SEMICONDUCTORS
元件分類： 鎖存器
英文描述： 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
封裝： 13.50 X 5.50 MM, 1.05 MM HEIGHT, PLASTIC, SOT-536-1, LFBGA-96
文件頁數(shù)： 19/28頁
文件大?。?/td> 153K
代理商： SSTUA32866EC,557
SSTUA32866_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 26 March 2007
26 of 28
NXP Semiconductors
SSTUA32866
1.8 V DDR2-667 congurable registered buffer with parity
15. Revision history
Table 14.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
SSTUA32866_2
20070326
Product data sheet
-
SSTUA32866_1
Modications:
The format of this data sheet has been redesigned to comply with the new identity guidelines of
NXP Semiconductors.
Legal texts have been adapted to the new company name where appropriate.
3rd paragraph, 2nd sentence of Section 7 “Functional description”: changed “... and CK going
LOW.” to “... and CK going LOW.”
– changed Parameter for VI to “input voltage”; moved “receiver” to Conditions
– changed Parameter for VO to “output voltage”; moved “driver” to Conditions
– changed Parameter for IO to “output current”; moved “continuous” to Conditions
Table 6 “Recommended operating conditions”: changed symbol “VTT” to “VT”
– Symbol IDD: changed Parameter to “supply current”; moved “static standby” and “static
operating” to Conditions
– IDD, supply current, static standby: changed Max value from “100 A” to “2 mA”
– Symbol IDDD: changed Parameter to “dynamic operating current per MHz”; moved “clock only”,
and “per each data input, 1 : 1 mode”, and “per each data input, 1 : 2 mode” to Conditions
– Symbol Ci: changed Parameter to “input capacitance”; moved “data and CSR inputs”,
“CK and CK inputs”, and “RESET input” to Conditions
Table 8 “Timing requirements”, Symbol tW: changed Parameter to “pulse width”; moved “CK, CK
HIGH or LOW” to Conditions
– changed Symbol “fMAX” to “fmax”
– changed Parameter for tPDM to “peak propagation delay”; moved “single bit switching” to
Conditions
– changed Parameter for tPDMSS to “simultaneous switching peak propagation delay”
(throughout data sheet): changed “VDD/2” to “0.5VDD”
SSTUA32866_1
(9397 750 14759)
20050715
Product data sheet
-
相關PDF資料
PDF描述
SSTUA32866EC/G,551 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
SSTUA32866EC/G,557 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
SSTUAF32866BHLFT 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96
SSTUAF32869AHLFT 32869 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA150
SSTUB32864EC/G 32864 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
相關代理商/技術參數(shù)
參數(shù)描述
SSTUA32866EC-G 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-667 RDIMM applications
SSTUA32S865 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-667 RDIMM applications
SSTUA32S865BHLF 功能描述:IC REGIST BUFF 25BIT DDR 160BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:- 產(chǎn)品變化通告:Product Discontinuation 25/Apr/2012 標準包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數(shù):14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應商設備封裝:48-TSSOP 包裝:帶卷 (TR)
SSTUA32S865BHLFT 功能描述:IC REGIST BUFF 25BIT DDR 160BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:- 產(chǎn)品變化通告:Product Discontinuation 25/Apr/2012 標準包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數(shù):14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應商設備封裝:48-TSSOP 包裝:帶卷 (TR)
SSTUA32S865ET 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-667 RDIMM applications
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*