參數(shù)資料
型號(hào): SST89V54RD2-33-I-TQJ
廠商: SILICON STORAGE TECHNOLOGY INC
元件分類: 微控制器/微處理器
英文描述: FlashFlex51 MCU
中文描述: 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQFP44
封裝: MS-026ACB, TQFP-44
文件頁(yè)數(shù): 30/91頁(yè)
文件大?。?/td> 984K
代理商: SST89V54RD2-33-I-TQJ
30
Preliminary Specifications
FlashFlex51 MCU
SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2
SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2
2004 Silicon Storage Technology, Inc.
S71255-00-000
3/04
Symbol
SPIE
SPE
Function
If both SPIE and ES are set to one, SPI interrupts are enabled.
SPI enable bit.
0: Disables SPI.
1: Enables SPI and connects SS#, MOSI, MISO, and SCK to pins P1.4, P1.5, P1.6, P1.7.
Data Transmission Order.
0: MSB first in data transmission.
1: LSB first in data transmission.
Master/Slave select.
0: Selects Slave mode.
1: Selects Master mode.
Clock Polarity
0: SCK is low when idle (Active High).
1: SCK is high when idle (Active Low).
Clock Phase control bit.
0: Shift triggered on the leading edge of the clock.
1: Shift triggered on the trailing edge of the clock.
SPI Clock Rate Select bits. These two bits control the SCK rate of the device
configured as master. SPR1 and SPR0 have no effect on the slave. The relationship
between SCK and the oscillator frequency, f
OSC
, is as follows:
DORD
MSTR
CPOL
CPHA
SPR1, SPR0
Symbol
SPIF
Function
SPI Interrupt Flag.
Upon completion of data transfer, this bit is set to 1.
If SPIE =1 and ES =1, an interrupt is then generated.
This bit is cleared by software.
Write Collision Flag.
Set if the SPI data register is written to during data transfer.
This bit is cleared by software.
WCOL
SPI Control Register (SPCR)
Location
D5H
7
6
5
4
3
2
1
0
Reset Value
00H
SPIE
SPE
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
SPR1
0
0
1
1
SPR0
0
1
0
1
SCK = f
OSC
divided by
4
16
64
128
SPI Status Register (SPSR)
Location
AAH
7
6
5
-
4
-
3
-
2
-
1
-
0
-
Reset Value
00xxxxxxb
SPIF
WCOL
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