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參數資料
| 型號： | SST89E54RC-33-C-PIE |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MS-011AC, DIP-40 |
| 文件頁數： | 33/57頁 |
| 文件大?。?/td> | 652K |
| 代理商： | SST89E54RC-33-C-PIE |
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Data Sheet
FlashFlex MCU
SST89E52RC / SST89E54RC
39
2007 Silicon Storage Technology, Inc.
S71259-04-000
1/07
9.0 RESET
A system reset initializes the MCU and begins program
execution at program memory location 0000H or the boot
vector address. The reset input for the device is the RST
pin. In order to reset the device, a logic level high must be
applied to the RST pin for at least two machine cycles (24
clocks), after the oscillator becomes stable. ALE and
PSEN# are weakly pulled high during reset. During reset,
ALE and PSEN# output a high level in order to perform a
proper reset. This level must not be affected by external
element. A system reset will not affect the 512 Bytes of on-
chip RAM while the device is running, however, the con-
tents of the on-chip RAM during power up are indetermi-
nate. Following reset, all Special Function Registers (SFR)
9.1 Power-on Reset
At initial power up, the port pins will be in a random state
until the oscillator has started and the internal reset algo-
rithm has weakly pulled all pins high.
When power is applied to the device, the RST pin must be
held high long enough for the oscillator to start up (usually
several milliseconds for a low frequency crystal), in addition
to two machine cycles for a valid power-on reset. An exam-
ple of a method to extend the RST signal is to implement a
RC circuit by connecting the RST pin to VDD through a 10
F capacitor and to VSS through an 8.2KΩ resistor as
shown in Figure 9-1. Note that if an RC circuit is being
used, provisions should be made to ensure the VDD rise
time does not exceed 1 millisecond and the oscillator start-
up time does not exceed 10 milliseconds.
For a low frequency oscillator with slow start-up time the
reset signal must be extended in order to account for the
slow start-up time. This method maintains the necessary
relationship between VDD and RST to avoid programming
at an indeterminate location. The POF flag in the PCON
register is set to indicate an initial power up condition. The
POF flag will remain active until cleared by software.
Please refer to Section 3.5, PCON register definition, for
detailed information.
For more information on system level design techniques,
please review the Design Considerations for the SST
FlashFlex Family Microcontroller application note.
FIGURE
9-1: Power-on Reset Circuit
1259 F25.2
VDD
10F
+
-
8.2K
SST89E54RC
SST89E52RC
RST
XTAL2
XTAL1
C1
C2
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相關代理商/技術參數 |
參數描述 |
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| SST89E54RD | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:FlashFlex MCU |
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| SST89E54RD2-33-C-NI | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:FlashFlex51 MCU |
| SST89E54RD2-33-C-NIE1 | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:FlashFlex51 MCU |
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