參數(shù)資料
型號(hào)： SST65P542R-8-C-SG
廠商： SILICON STORAGE TECHNOLOGY INC
元件分類： 微控制器/微處理器
英文描述： Remote Controller MCU
中文描述： 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PDSO28
封裝： MS-013AE, SOIC-28
文件頁(yè)數(shù)： 17/40頁(yè)
文件大?。?/td> 538K
代理商： SST65P542R-8-C-SG
Advance Information
Remote Controller MCU
SST65P542R
17
2001 Silicon Storage Technology, Inc.
S71170-03-000
12/01 368
Symbol
EOC
Function
End of modulation cycle status bit. This bit is read only. EOC is set when a match occurs
between the contents of the space period register SREG and the down counter. At the end of
cycle, the counter is initialized with the contents of the mark period buffer, MBUFF and SREG is
loaded with the space period buffer SBUFF. This flag is cleared by reading the MCSR followed
by an access of MDR2 or MDR3. EOC is cleared by reset.
0: current modulation cycle in progress.
1: end of modulator cycle has occurred.
Divide by two scaler bit. The divide-by-two prescaler causes the CMT to be clocked at the bus
rate, when the two times of bus rate is enabled and the F
OSC
is disabled. Since this bit is not
double buffered, this bit should not be set during a transmission.
0: divide-by-two prescaler disabled.
1: divide-by-two prescaler enabled.
External Interrupt Mask bit. This bit is used to mask IRQ and keyscan interrupts. This bit is
cleared by reset.
0: IRQ and keyscan interrupts enabled.
1: IRQ and keyscan interrupts disabled.
Extended Space Enable bit. For detailed description of extended space operation, please refer
to
65P542R Programming User’s Manual.
0: Extended space disabled.
1: Extended space enabled
Baseband Enable bit. This bit disables the carrier generator and forces the carrier output high for
generation of baseband protocols. When BASE is cleared, the carrier generator is enabled and
the carrier output toggles at the frequency determined by values stored in the carrier data
registers. This bit is cleared by reset. This bit is not double buffered and should not be written
during a transmission.
0: Baseband disabled.
1: Baseband enabled.
Mode select bit. This bit is cleared by reset. This bit is not double buffered and should not be
written during a transmission.
0: CMT operates in Time mode.
1: CMT operates in FSK mode.
Interrupt enable bit. Interrupt request will be generated when EOC is set and EOCIE is set.
Otherwise, interrupt will not be generated
0: interrupt disabled.
1: interrupt enabled.
Modulator and carrier generator enable bit. Set this bit will initialize the carrier and modulator and
will enable all clocks. Once enabled, the carrier generator and modulator will function
continuously.
0: if this bit is zero, the current modulator cycle will be allowed to expire before all carrier and
modulator clocks are disabled and the modulator output is forced low. To prevent spurious
operation, the user should initialize all data and control registers before enabling the system.
This bit is cleared by reset.
All bits except Bit 0 can be used for both reading and writing.
1: Modulator and carrier generator enabled.
DIV2
EIMSK
EXSPC
BASE
MODE
EOCIE
MCGEN
Modulator Control and Status Register (MCSR)
Location
0014H
7
6
5
4
3
2
1
0
Reset Value
00H
EOC
DIV2
EIMSK
EXSPC
BASE
MODE
EOCIE
MCGEN
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