參數(shù)資料
型號: SST49LF080A-33-4C-WH
廠商: SILICON STORAGE TECHNOLOGY INC
元件分類: PROM
英文描述: 8 Mbit LPC Flash
中文描述: 1M X 8 FLASH 3V PROM, 11 ns, PDSO32
封裝: 8 X 14 MM, MO-142BA, TSOP1-32
文件頁數(shù): 18/49頁
文件大?。?/td> 579K
代理商: SST49LF080A-33-4C-WH
18
Data Sheet
8 Mbit LPC Flash
SST49LF080A
2003 Silicon Storage Technology, Inc.
S71235-00-000
4/03
Write Operation Status Detection
The SST49LF080A devices provide two software means to
detect the completion of a Write (Program or Erase) cycle,
in order to optimize the system Write cycle time. The soft-
ware detection includes two status bits: Data# Polling D[7]
and Toggle Bit D[6]. The End-of-Write detection mode is
enabled after the rising edge of WE# which initiates the
internal Program or Erase operation.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con-
flict with either D[7] or D[6]. In order to prevent spurious
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the Write cycle, otherwise the rejec-
tion is valid.
Data# Polling (DQ
7
)
When the SST49LF080A device is in the internal Program
operation, any attempt to read DQ
7
will produce the com-
plement of the true data. Once the Program operation is
completed, DQ
7
will produce true data. Note that even
though DQ
7
may have valid data immediately following the
completion of an internal Write operation, the remaining
data outputs may still be invalid: valid data on the entire
data bus will appear in subsequent successive Read
cycles after an interval of 1 μs. During internal Erase opera-
tion, any attempt to read DQ
7
will produce a ‘0’. Once the
internal Erase operation is completed, DQ
7
will produce a
‘1’. The Data# Polling is valid after the rising edge of fourth
WE# pulse for Program operation. For Sector-, Block-, or
Chip-Erase, the Data# Polling is valid after the rising edge
of sixth WE# pulse. See Figure 19 for Data# Polling timing
diagram and Figure 34 for a flowchart. Proper status will
not be given using Data# Polling if the address is in the
invalid range.
Toggle Bit (DQ
6
)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
6
will produce alternating ‘0’s
and ‘1’s, i.e., toggling between 0 and 1. When the internal
Program or Erase operation is completed, the toggling will
stop. The device is then ready for the next operation. The
Toggle Bit is valid after the rising edge of fourth WE# pulse
for Program operation. For Sector-, Block-, or Chip-Erase,
the Toggle Bit is valid after the rising edge of sixth WE#
pulse. See Figure 20 for Toggle Bit timing diagram and Fig-
ure 34 for a flowchart.
TABLE 10: O
PERATION
M
ODES
S
ELECTION
(PP M
ODE
)
Mode
Read
Program
Erase
RST#
V
IH
V
IH
V
IH
OE#
V
IL
V
IH
V
IH
WE#
V
IH
V
IL
V
IL
DQ
D
OUT
D
IN
X
1
Address
A
IN
A
IN
Sector or Block address,
XXH for Chip-Erase
X
X
X
See Table 11
1. X can be V
IL
or V
IH
, but no other value.
2. Device ID = 5BH for SST49LF080A
Reset
Write Inhibit
V
IL
V
IH
X
V
IH
X
V
IL
X
V
IL
X
X
High Z
High Z/D
OUT
High Z/D
OUT
Manufacturer’s ID (BFH)
Device ID
2
V
IH
V
IH
Product Identification
T10.0 1235
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