參數(shù)資料
型號: SST49LF080A-33-4C-WH
廠商: SILICON STORAGE TECHNOLOGY INC
元件分類: PROM
英文描述: 8 Mbit LPC Flash
中文描述: 1M X 8 FLASH 3V PROM, 11 ns, PDSO32
封裝: 8 X 14 MM, MO-142BA, TSOP1-32
文件頁數(shù): 13/49頁
文件大小: 579K
代理商: SST49LF080A-33-4C-WH
Data Sheet
8 Mbit LPC Flash
SST49LF080A
13
2003 Silicon Storage Technology, Inc.
S71235-00-000
4/03
FIGURE 5: LPC W
RITE
C
YCLE
W
AVEFORM
TABLE
6: LPC W
RITE
C
YCLE
Clock
Cycle
1
Field
Name
START
Field Contents
LAD[3:0]
1
0000
LAD[3:0]
Direction
IN
Comments
LFRAME# must be active (low) for the part to respond.
Only the last start field (before LFRAME# transitions
high) should be recognized.
Indicates the type of cycle. Bits 3:2 must be “01b” for
memory cycle. Bit 1 indicates the type of transfer “1”
for Write. Bit 0 is reserved.
Address Phase for Memory Cycle. LPC protocol sup-
ports a 32-bit address phase. YYYY is one nibble of
the entire address. Addresses are transferred most-
significant nibble first. See Table 3 for address bits def-
inition and Table 4 for valid memory address range.
This field is the least-significant nibble of the data byte.
This field is the most-significant nibble of the data byte.
In this clock cycle, the host has driven the bus to all ‘1’s
and then floats the bus. This is the first part of the bus
“turnaround cycle.”
The SST49LF080A takes control of the bus during this
cycle.
The SST49LF080A outputs the values 0000, indicat-
ing that it has received data or a flash command.
In this clock cycle, the SST49LF080A has driven the
bus to all ‘1’s and then floats the bus. This is the first
part of the bus “turnaround cycle.”
Host resumes control of the bus during this cycle.
2
CYCTYPE +
DIR
011X
IN
3-10
ADDRESS
YYYY
IN
11
12
13
DATA
DATA
TAR0
ZZZZ
ZZZZ
1111
IN
IN
IN then Float
14
TAR1
1111 (float)
Float then OUT
15
SYNC
0000
OUT
16
TAR0
1111
OUT then Float
17
TAR1
1111 (float)
Float then IN
T6.0 1235
1. Field contents are valid on the rising edge of the present clock cycle.
1235 F05.0
LFRAME#
LAD[3:0]
0000b
011Xb
A[23:20]
A[19:16]
A[3:0]
A[7:4]
A[11:8]
A[15:12]
1111b
Tri-State
2 Clocks
TAR0
Load Address in 8 Clocks
Address
1 Clock
1 Clock
Start
CYC+
DIR
TAR
1 Clock
Sync
Data
Load Data in 2 Clocks
0000b
D[7:4]
D[3:0]
LCLK
CE#
A[31:28] A[27:24]
Data
TAR1
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