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參數(shù)資料
| 型號： | SST49LF004B-33-4C-NHE |
| 廠商： | SILICON STORAGE TECHNOLOGY INC |
| 元件分類： | PROM |
| 英文描述： | 4 Mbit LPC Firmware Flash |
| 中文描述： | 512K X 8 FLASH 3V PROM, 11 ns, PQCC32 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MS-016AE, LCC-32 |
| 文件頁數(shù)： | 12/39頁 |
| 文件大?。?/td> | 460K |
| 代理商： | SST49LF004B-33-4C-NHE |
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12
Data Sheet
4 Mbit LPC Firmware Flash
SST49LF004B
2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
Firmware Memory Read Cycle
FIGURE 4: F
IRMWARE
M
EMORY
R
EAD
C
YCLE
W
AVEFORM
TABLE
4: F
IRMWARE
M
EMORY
R
EAD
C
YCLE
F
IELD
D
EFINITIONS
Clock
Cycle
1
Field
Name
START
Field Contents
LAD[3:0]
1
1101
1. Field contents are valid on the rising edge of the present clock cycle.
LAD[3:0]
Direction
IN
Comments
LFRAME# must be active (low) for the device to respond.
Only the last field latched before LFRAME# transitions high
will be recognized. The START field contents (1101b) indi-
cate a Firmware Memory Read cycle.
Indicates which SST49LF004B device should respond. If the
IDSEL (ID select) field matches the value of ID[3:0], the device
will respond to the LPC bus cycle.
These seven clock cycles make up the 28-bit memory
address. YYYY is one nibble of the entire address.
Addresses are transferred most-significant nibble first.
The MSIZE field indicates how many bytes will be trans-
ferred during multi-byte operations. The SST49LF004B only
supports single-byte operation. MSIZE=0000b
In this clock cycle, the master (Intel ICH) has driven the bus
to all ‘1’s and then floats the bus, prior to the next clock
cycle. This is the first part of the bus “turnaround cycle.”
The SST49LF004B takes control of the bus during this
cycle.
During this clock cycle, the device generates a “ready sync”
(RSYNC) indicating that the device has received the input
data.
ZZZZ is the least-significant nibble of the data byte.
ZZZZ is the most-significant nibble of the data byte.
In this clock cycle, the SST49LF004B drives the bus to all
ones and then floats the bus prior to the next clock cycle.
This is the first part of the bus “turnaround cycle.”
The host resumes control of the bus during this cycle.
2
IDSEL
0000 to 1111
IN
3-9
MADDR
YYYY
IN
10
MSIZE
0000 (1 Byte)
IN
11
TAR0
1111
IN then Float
12
TAR1
1111 (float)
Float then
OUT
OUT
13
RSYNC
0000 (READY)
14
15
16
DATA
DATA
TAR0
ZZZZ
ZZZZ
1111
OUT
OUT
OUT then
Float
17
TAR1
1111 (float)
Float then IN
T4.0 1232
1232 F03.0
LFRAME#
LAD[3:0]
1101b
0000b
A[23:20]
A[19:16]
A[3:0]
A[7:4]
A[11:8]
A[15:12]
MADDR
Start
IDSEL
MSIZE
LCLK
A[27:24]
0000b
RSYNC
TAR1
TAR0
TAR
D[7:4]
Tri-State
D[3:0]
0000b
1111b
DATA
相關PDF資料 |
PDF描述 |
|---|---|
| SST49LF040 | 4 Mbit LPC Flash |
| SST49LF020 | 2 Megabit LPC Flash |
| SST49LF020-33-4C-NH | 2 Megabit LPC Flash |
| SST49LF020-33-4C-WH | 2 Megabit LPC Flash |
| SST49LF040-33-4C-NH | 4 Mbit LPC Flash |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SST49LF004B334CNHT | 制造商:SST 功能描述:NEW |
| SST49LF004B-33-4C-WHE | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:4 Mbit Firmware Hub |
| SST49LF004C | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:4 Mbit / 8 Mbit LPC Serial Flash |
| SST49LF004C-33-4C-NHE | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:4 Mbit / 8 Mbit LPC Serial Flash |
| SST49LF004C-33-4C-WHE | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:4 Mbit / 8 Mbit LPC Serial Flash |
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