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參數(shù)資料
| 型號： | SST49LF004B-33-4C-NHE |
| 廠商： | SILICON STORAGE TECHNOLOGY INC |
| 元件分類： | PROM |
| 英文描述： | 4 Mbit LPC Firmware Flash |
| 中文描述： | 512K X 8 FLASH 3V PROM, 11 ns, PQCC32 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MS-016AE, LCC-32 |
| 文件頁數(shù)： | 11/39頁 |
| 文件大?。?/td> | 460K |
| 代理商： | SST49LF004B-33-4C-NHE |
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Data Sheet
4 Mbit LPC Firmware Flash
SST49LF004B
11
2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
MODE SELECTION
The SST49LF004B flash memory device operates in two
distinct interface modes: the LPC mode and the Parallel
Programming (PP) mode. In LPC mode, communication
between the Host and the SST49LF004B occurs via the 4-
bit I/O communication signals, LAD[3:0], and LFRAME#. In
PP mode, the device is controlled via the 11 addresses,
A
10
-A
0
, and 8 I/O, DQ
7
-DQ
0
, signals. The address inputs
are multiplexed in row and column selected by control sig-
nal R/C# pin. The row addresses are mapped to the lower
internal addresses (A
10-0
), and the column addresses are
mapped to the higher internal addresses (A
18-11
). See Fig-
ure 3, Device Memory Map, for address assignments.
LPC MODE
Device Operation
The LPC mode uses a 5-signal communication interface
consisting of one control line, LFRAME#, which is driven by
the host to start or abort a bus cycle, and a 4-bit data bus,
LAD[3:0], which is used to communicate cycle type, cycle
direction, ID selection, address, data and sync fields. The
device enters standby mode when LFRAME# is high and
no internal operation is in progress.
The SST49LF004B supports both single-byte Firmware
Memory Read/Write cycles and single-byte LPC Memory
Read/Write cycles as defined in Intel’s Low-Pin-Count
Interface Specification, Revision 1.1. The host drives
LFRAME# low for one or more clock cycles to initiate an
LPC cycle. The last latched value of LAD[3:0] before
LFRAME# is the START value. The START value deter-
mines whether the SST49LF004B will respond to a Firm-
ware Memory Read/Write cycle or a LPC Memory Read/
Write cycle as defined in Table 3.
See following sections for details of Firmware Memory and
LPC Memory cycle types. JEDEC standard SDP (Soft-
ware Data Protection) Program and Erase command
sequences are used to initiate Firmware and LPC Memory
Program and Erase operations. See Table 12 for a listing
of Program and Erase commands. Chip-Erase is only
available in PP mode.
TABLE
3: F
IRMWARE
AND
LPC M
EMORY
C
YCLES
START F
IELD
D
EFINITION
START
Value
0000
Definition
Start of an LPC memory cycle. The direction
(Read or Write) is determined by the second field
of the LPC cycle.
Start of a Firmware Memory Read cycle
Start of a Firmware Memory Write cycle
1101
1110
T3.0 1232
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SST49LF040 | 4 Mbit LPC Flash |
| SST49LF020 | 2 Megabit LPC Flash |
| SST49LF020-33-4C-NH | 2 Megabit LPC Flash |
| SST49LF020-33-4C-WH | 2 Megabit LPC Flash |
| SST49LF040-33-4C-NH | 4 Mbit LPC Flash |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SST49LF004B334CNHT | 制造商:SST 功能描述:NEW |
| SST49LF004B-33-4C-WHE | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:4 Mbit Firmware Hub |
| SST49LF004C | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:4 Mbit / 8 Mbit LPC Serial Flash |
| SST49LF004C-33-4C-NHE | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:4 Mbit / 8 Mbit LPC Serial Flash |
| SST49LF004C-33-4C-WHE | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:4 Mbit / 8 Mbit LPC Serial Flash |
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