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參數(shù)資料
| 型號： | SST39WF800B-70-4I-B3KE |
| 廠商： | SILICON STORAGE TECHNOLOGY INC |
| 元件分類： | PROM |
| 英文描述： | 64 Mbit (x16) Multi-Purpose Flash Plus |
| 中文描述： | 512K X 16 FLASH 1.8V PROM, 70 ns, PBGA48 |
| 封裝： | 6 X 8 MM, 0.80 MM PITCH, ROHS COMPLIANT, MO-210AB-1, TFBGA-48 |
| 文件頁數(shù)： | 3/26頁 |
| 文件大?。?/td> | 773K |
| 代理商： | SST39WF800B-70-4I-B3KE |
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Data Sheet
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
3
2007 Silicon Storage Technology, Inc.
S71344-00-000
2/07
Write Operation Status Detection
To optimize the system write cycle time, the
SST39WF800B provides two software means to detect the
completion of a Program or Erase write cycle. The software
detection includes two status bits—Data# Polling (DQ
7
)
and Toggle Bit (DQ
6
). The End-of-Write detection mode is
enabled after the rising edge of WE#, which initiates the
internal Program or Erase operation.
The completion of the nonvolatile Write is asynchronous
with the system; therefore, either a Data# Polling or Toggle
Bit read may occur simultaneously with the completion of
the Write cycle. If this occurs, the system may get an erro-
neous result, i.e., valid data may appear to conflict with
either DQ
7
or DQ
6
. To prevent spurious rejection in the
event of an erroneous result, the software routine must
include a loop to read the accessed location an additional
two (2) times. If both Reads are valid, then the device has
completed the Write cycle, otherwise the rejection is valid.
Data# Polling (DQ
7
)
When the SST39WF800B is in the internal Program oper-
ation, any attempt to read DQ
7
will produce the comple-
ment of the true data. Once the Program operation is
complete, DQ
7
will produce true data.
Although DQ
7
may have valid data immediately following
the completion of an internal Write operation, the remain-
ing data outputs may still be invalid. Valid data on the
entire data bus will appear in subsequent successive
Read
cycles after an interval of 1 μs
.
During an internal
Erase operation, any attempt to read DQ
7
will produce a
‘0’. Once the internal Erase operation is complete, DQ
7
will
produce a ‘1’.
The Data# Polling is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-,
Block-, or Chip-Erase, the Data# Polling is valid after the
rising edge of sixth WE# (or CE#) pulse. See Figure 7 for
Data# Polling timing diagram and Figure 17 for a flowchart.
Toggle Bit (DQ
6
)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
6
will produce alternating ‘1’s
and ‘0’s, i.e., toggling between ‘1’ and ‘0’.
When the Program or Erase operation is complete, the
DQ
6
bit will stop toggling and the device is ready for the
next operation.
The Toggle Bit is valid after the rising edge of fourth WE#
(or CE#) pulse for Program operation. For Sector-, Block-
or Chip-Erase, the Toggle Bit is valid after the rising edge of
sixth WE# (or CE#) pulse. See Figure 0-1 for Toggle Bit
timing diagram and Figure 17 for a flowchart.
Data Protection
The SST39WF800B provides both hardware and software
features to protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a write cycle.
V
DD
Power Up/Down Detection: The Write operation is
inhibited when V
DD
is less than 1.0V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Software Data Protection (SDP)
The SST39WF800B provides the JEDEC approved Soft-
ware Data Protection scheme for all data alteration opera-
tions, i.e., Program and Erase. Any Program operation
requires the inclusion of the three-byte sequence. The
three-byte load sequence is used to initiate the Program
operation, providing optimal protection from inadvertent
Write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion of
six-byte sequence. This group of devices are shipped with
the Software Data Protection permanently enabled. See
Table 4 for the specific software command codes. During
SDP command sequence, invalid commands will abort the
device to Read mode within T
RC
. The contents of DQ
15
-
DQ
8
can be V
IL
or V
IH
, but no other value, during any SDP
command sequence.
Common Flash Memory Interface (CFI)
The SST39WF800A contains the CFI information that
describes the characteristics of the device, and supports
both the original SST CFI Query mode implementation for
compatibility with existing SST devices, as well as the gen-
eral CFI Query mode.
To enter the SST CFI Query mode, the system must write
the three-byte sequence, same as the Product ID Entry
command, with 98H (CFI Query command) to address
5555H in the last byte sequence.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SST39WF800B-70-4I-B3KE-T | 功能描述:閃存 1.65 to 1.95V 8Mbit Multi-Purpose 閃存 RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| SST39WF800B-70-4I-C2QE | 功能描述:閃存 1.65 to 1.95V 8Mbit Multi-Purpose 閃存 RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| SST39WF800B-70-4I-MAQE | 功能描述:閃存 1.65 to 1.95V 8Mbit Multi-Purpose 閃存 RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| SST3A(T/R) | 制造商:Bel Fuse 功能描述:FUSE SST SERIES |
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