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參數(shù)資料
| 型號： | SST39WF800B-70-4I-B3KE |
| 廠商： | SILICON STORAGE TECHNOLOGY INC |
| 元件分類： | PROM |
| 英文描述： | 64 Mbit (x16) Multi-Purpose Flash Plus |
| 中文描述： | 512K X 16 FLASH 1.8V PROM, 70 ns, PBGA48 |
| 封裝： | 6 X 8 MM, 0.80 MM PITCH, ROHS COMPLIANT, MO-210AB-1, TFBGA-48 |
| 文件頁數(shù)： | 2/26頁 |
| 文件大?。?/td> | 773K |
| 代理商： | SST39WF800B-70-4I-B3KE |
2
Data Sheet
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
2007 Silicon Storage Technology, Inc.
S71344-00-000
2/07
Device Operation
Commands, which are used to initiate the memory opera-
tion functions of the device, are written to the device using
standard microprocessor write sequences. A command is
written by asserting WE# low while keeping CE# low. The
address bus is latched on the falling edge of WE# or CE#,
whichever occurs last. The data bus is latched on the rising
edge of WE# or CE#, whichever occurs first.
Read
The Read operation of the SST39WF800B is controlled by
CE# and OE#; both have to be low for the system to obtain
data from the outputs.
CE# is used for device selection. When CE# is high, the
chip is deselected and only standby power is consumed.
OE# is the output control and is used to gate data from the
output pins. The data bus is in high impedance state when
either CE# or OE# is high. See Figure 4.
Word-Program Operation
The SST39WF800B is programmed on a word-by-word
basis. The sector where the word exists must be fully
erased before programming.
Programming is accomplished in three steps:
1. Load the three-byte sequence for Software Data
Protection.
2. Load word address and word data. During the
Word-Program operation, the addresses are
latched on the falling edge of either CE# or WE#,
whichever occurs last. The data is latched on the
rising edge of either CE# or WE#, whichever
occurs first.
3. Initiate the internal Program operation after the
rising edge of the fourth WE# or CE#, whichever
occurs first. Once initiated, the Program operation
will be completed within 40 μs. See Figures 5 and
6 for WE# and CE# controlled Program operation
timing diagrams and Figure 16 for flowcharts.
During the Program operation, the only valid reads are
Data# Polling and Toggle Bit. During the internal Program
operation, the host is free to perform additional tasks. Any
commands issued during the internal Program operation
are ignored.
Sector-/Block-Erase Operation
The SST39WF800B offers both Sector-Erase and Block-
Erase modes which allow the system to erase the device
on a sector-by-sector, or block-by-block, basis.
The sector architecture is based on uniform sector size of 2
KWord. Initiate the Sector-Erase operation by executing a
six-byte command sequence with Sector-Erase command
(30H) and sector address (SA) in the last bus cycle.
The Block-Erase mode is based on uniform block size of
32 KWord. Initiate the Block-Erase operation by executing
a six-byte command sequence with Block-Erase command
(50H) and block address (BA) in the last bus cycle.
The sector or block address is latched on the falling edge of
the sixth WE# pulse, while the command (30H or 50H) is
latched on the rising edge of the sixth WE# pulse. The
internal Erase operation begins after the sixth WE# pulse.
The End-of-Erase operation can be determined using
either Data# Polling or Toggle Bit methods. See Figures 9
and 10 for timing waveforms. Any commands issued during
the Sector- or Block-Erase operation are ignored.
Chip-Erase Operation
The SST39WF800B provides a Chip-Erase operation,
which allows the user to erase the entire memory array to
the ‘1’ state. This is useful when the entire device must be
quickly erased.
Initiate the Chip-Erase operation by executing a six-byte
command sequence with Chip-Erase command (10H) at
address 5555H in the last byte sequence.
The Erase operation begins with the rising edge of the sixth
WE# or CE#, whichever occurs first. During the Erase
operation, the only valid read is Toggle Bit or Data# Polling.
See Table 4 for the command sequence, Figure 8 for the
timing diagram, and Figure 19 for the flowchart. Any com-
mands issued during the Chip-Erase operation are
ignored.
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| SST39WF800B-70-4I-B3KE-T | 功能描述:閃存 1.65 to 1.95V 8Mbit Multi-Purpose 閃存 RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| SST39WF800B-70-4I-C2QE | 功能描述:閃存 1.65 to 1.95V 8Mbit Multi-Purpose 閃存 RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| SST39WF800B-70-4I-MAQE | 功能描述:閃存 1.65 to 1.95V 8Mbit Multi-Purpose 閃存 RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
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