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參數(shù)資料
| 型號： | SST30VR021-500-E-WH |
| 廠商： | SILICON STORAGE TECHNOLOGY INC |
| 元件分類： | 存儲器 |
| 英文描述： | 2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM ROM/RAM Combo |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PDSO32 |
| 封裝： | 8 X 14 MM, TSOP1-32 |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 111K |
| 代理商： | SST30VR021-500-E-WH |
4
Data Sheet
2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM
ROM/RAM Combo
SST30VR021 / SST30VR022 / SST30VR023
2001 Silicon Storage Technology, Inc.
S71135-02-000
4/01
380
FIGURE 2: AC I
NPUT
/O
UTPUT
R
EFERENCE
W
AVEFORMS
FIGURE 3: A T
EST
L
OAD
E
XAMPLE
TABLE
4: C
APACITANCE
(Ta = 25
°
C, f=1 Mhz)
Parameter
C
I/O1
C
IN1
Description
I/O Pin Capacitance
Input Capacitance
Test Condition
V
I/O
= 0V
V
IN
= 0V
Maximum
8 pF
6 pF
T4.1 380
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
380 ILL F08.0
REFERENCE POINTS
OUTPUT
INPUT
VIT
VIHT
VILT
VOT
AC test inputs are driven at V
IHT
(0.9 V
DD
) for a logic
“
1
”
and V
ILT
(0.1 V
DD
) for a logic
“
0
”
. Measurement reference points
for inputs and outputs are V
IT
(0.5 V
DD
) and V
OT
(0.5 V
DD
). Input rise and fall times (10%
90%) are <5 ns.
Note:
V
IT
- V
INPUT
Test
V
OT
- V
OUTPUT
Test
V
IHT
- V
INPUT
HIGH Test
V
ILT
- V
INPUT
LOW Test
380 ILL F09.0
TO TESTER
TO DUT
CL
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| SST30VR041-500-E-WH | 4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SST30VR021-500-I-KH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SRAM/ROM |
| SST30VR021-500-I-WH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SRAM/ROM |
| SST30VR021-70-C-WH | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM ROM/RAM Combo |
| SST30VR021-70-E-WH | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM ROM/RAM Combo |
| SST30VR022 | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM ROM/RAM Combo |
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