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參數(shù)資料
| 型號： | SST29VF040-55-4C-WHE |
| 廠商： | SILICON STORAGE TECHNOLOGY INC |
| 元件分類： | PROM |
| 英文描述： | 4 Mbit (x8) Small-Sector Flash |
| 中文描述： | 512K X 8 FLASH 2.7V PROM, 55 ns, PDSO32 |
| 封裝： | 8 X 14 MM, MO-142BA, TSOP1-32 |
| 文件頁數(shù)： | 3/22頁 |
| 文件大小： | 277K |
| 代理商： | SST29VF040-55-4C-WHE |
Data Sheet
4 Mbit Small-Sector Flash
SST29SF040 / SST29VF040
3
2004 Silicon Storage Technology, Inc.
S71160-10-000
2/04
Data# Polling (DQ
7
)
When the SST29SF040 and SST29VF040 devices are
in the internal Program operation, any attempt to read
DQ
7
will produce the complement of the true data. Once
the Program operation is completed, DQ
7
will produce
true data. Note that even though DQ
7
may have valid
data immediately following the completion of an internal
Write operation, the remaining data outputs may still be
invalid: valid data on the entire data bus will appear in
subsequent successive Read cycles after an interval of 1
μs. During internal Erase operation, any attempt to read
DQ
7
will produce a ‘0’. Once the internal Erase operation
is completed, DQ
7
will produce a ‘1’. The Data# Polling is
valid after the rising edge of fourth WE# (or CE#) pulse
for Program operation. For Sector- or Chip-Erase, the
Data# Polling is valid after the rising edge of sixth WE#
(or CE#) pulse. See Figure 6 for Data# Polling timing dia-
gram and Figure 16 for a flowchart.
Toggle Bit (DQ
6
)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
6
will produce alternating ‘0’s
and ‘1’s, i.e., toggling between 0 and 1. When the internal
Program or Erase operation is completed, the toggling will
stop. The device is then ready for the next operation. The
Toggle Bit is valid after the rising edge of fourth WE# (or
CE#) pulse for Program operation. For Sector or Chip-
Erase, the Toggle Bit is valid after the rising edge of sixth
WE# (or CE#) pulse. See Figure 7 for Toggle Bit timing dia-
gram and Figure 16 for a flowchart.
Data Protection
The SST29SF040 and SST29VF040 devices provide both
hardware and software features to protect nonvolatile data
from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a Write cycle.
V
DD
Power Up/Down Detection: The Write operation is
inhibited when V
DD
is less than 2.5V for SST29SF040. The
Write operation is inhibited when V
DD
is less than 1.5V. for
SST29VF040.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Software Data Protection (SDP)
The SST29SF040 and SST29VF040 provide the JEDEC
approved Software Data Protection scheme for all data
alteration operations, i.e., Program and Erase. Any Pro-
gram operation requires the inclusion of a series of three-
byte sequence. The three-byte load sequence is used to
initiate the Program operation, providing optimal protection
from inadvertent Write operations, e.g., during the system
power-up or power-down. Any Erase operation requires the
inclusion of a six-byte load sequence. These devices are
shipped with the Software Data Protection permanently
enabled. See Table 4 for the specific software command
codes. During SDP command sequence, invalid com-
mands will abort the device to read mode, within T
RC.
Product Identification
The Product Identification mode identifies the devices as
SST29SF040 or SST29VF040 and manufacturer as SST.
This mode may be accessed by software operations. Users
may use the Software Product Identification operation to
identify the part (i.e., using the device ID) when using multi-
ple manufacturers in the same socket. For details, see
Table 4 for software operation, Figure 10 for the Software ID
Entry and Read timing diagram and Figure 17 for the Soft-
ware ID Entry command sequence flowchart.
Product Identification Mode Exit/Reset
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read operation.
Please note that the Software ID Exit command is ignored
during an internal Program or Erase operation. See Table 4
for software command codes, Figure 11 for timing wave-
form, and Figure 17 for a flowchart.
TABLE
1: P
RODUCT
I
DENTIFICATION
Address
0000H
Data
BFH
Manufacturer’s ID
Device ID
SST29SF040
SST29VF040
0001H
0001H
13H
14H
T1.2 1160
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| SST29VF040-70-4C-NH | 功能描述:閃存 512K X 8 70ns RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| SST29VF040-70-4C-NHE | 功能描述:閃存 512K X 8 70ns RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| SST29VF040-70-4C-WH | 功能描述:閃存 512K X 8 70ns RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| SST29VF040-70-4C-WHE | 功能描述:閃存 512K X 8 70ns RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| SST29VF040-70-4I-NHE | 功能描述:閃存 512K x 8 70ns INDUSTRIAL TEMP RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
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