參數(shù)資料
型號(hào): SST25VF010-20-4C-QA-DD029
廠商: SILICON STORAGE TECHNOLOGY INC
元件分類: PROM
英文描述: 4 Mbit Uniform Sector, Serial Flash Memory
中文描述: 1M X 1 SPI BUS SERIAL EEPROM, DSO8
封裝: WSON-8
文件頁數(shù): 12/22頁
文件大?。?/td> 283K
代理商: SST25VF010-20-4C-QA-DD029
12
Data Sheet
1 Mbit SPI Serial Flash
SST25VF010
2003 Silicon Storage Technology, Inc.
S71233-01-000
8/03
Write-Enable (WREN)
The Write-Enable (WREN) instruction sets the Write-
Enable-Latch bit to 1 allowing Write operations to occur.
The WREN instruction must be executed prior to any Write
(Program/Erase) operation. CE# must be driven high
before the WREN instruction is executed.
FIGURE 11: W
RITE
E
NABLE
(WREN) S
EQUENCE
Write-Disable (WRDI)
The Write-Disable (WRDI) instruction resets the Write-
Enable-Latch bit and AAI bit to 0 disabling any new Write
operations from occurring. CE# must be driven high before
the WRDI instruction is executed.
FIGURE 12: W
RITE
D
ISABLE
(WRDI) S
EQUENCE
Enable-Write-Status-Register (EWSR)
The Enable-Write-Status-Register (EWSR) instruction
arms the Write-Status-Register (WRSR) instruction and
opens the status register for alteration. The Enable-Write-
Status-Register instruction does not have any effect and
will be wasted, if it is not followed immediately by the Write-
Status-Register (WRSR) instruction. CE# must be driven
low before the EWSR instruction is entered and must be
driven high before the EWSR instruction is executed.
CE#
SO
SI
SCK
0 1 2 3 4 5 6
7
06
HIGH IMPEDANCE
MODE 0
MODE 3
1233 F11.1
MSB
CE#
SO
SI
SCK
0 1 2 3 4 5 6
7
04
HIGH IMPEDANCE
MODE 0
MODE 3
1233 F12.1
MSB
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