- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374928 > SSD1828 (Electronic Theatre Controls, Inc.) LCD Segment / Common Driver with Controller CMOS PDF資料下載
參數(shù)資料
| 型號： | SSD1828 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LCD Segment / Common Driver with Controller CMOS |
| 中文描述： | LCD段/與普通的CMOS驅(qū)動(dòng)器控制器 |
| 文件頁數(shù)： | 26/43頁 |
| 文件大小： | 434K |
| 代理商： | SSD1828 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁當(dāng)前第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁
SSD1828
Rev 1.10
07/2002
SOLOMON
21
7.14 Read Status Byte
A 8 bits status byte will be placed to the data bus if a read operation is performed if D/C is low. The
status byte is defined as follow.
Table 8 - Read Status Byte
Bit Pattern
Command
Comment
BUSY ON RES 0
1000
Read Status
BUSY=0: Chip is idle
BUSY=1: Chip is executing instruction
ON=0: Display is OFF
ON=1: Display is ON
RES=0: Chip is idle
RES=1: Chip is executing reset
7.15 Data Read / Write
To read data from the GDDRAM, input High to R/W(WR#) pin and D/C pin for 6800-series parallel
mode. Low to E(RD#) pin and High to D/C pin for 8080-series parallel mode. No data read is provided
for serial mode. In normal mode, GDDRAM column address pointer will be increased by one
automatically after each data read. Also, a dummy read is required before the first data is read. See
Figure 3 in Functional Description.
To write data to the GDDRAM, input Low to R/W(WR#) pin and High to D/C pin for 6800-series
parallel mode. For serial interface, it will always be in write mode. GDDRAM column address pointer
will be increased by one automatically after each data write. The address will be reset to 0 in next data
read/write operation is executed when it is 95.
Table 9 - Address Increment Table
D/C
R/W (WR)
Comment
Address Increment
0
0
Write Command
No
0
1
Read Status
No
1
0
Write Data
Yes
1
1
Read Data
Yes
Address Increment is done automatically after data read/write. The column address pointer of
GDDRAM is also affected. It will be reset to 0 in next data read/write operation is executed when it is
95.
Table 10 - Commands Required for R/W (WR#) Actions on RAM
R/W (WR) Actions on RAMs
Commands Required
Read/write Data from/to GDDRAM
Set GDDRAM Page Address
Set GDDRAM Column Address
Read/Write Data
(1011X
3
X
2
X
1
X
0
)*
(0001X
3
X
2
X
1
X
0
)*
(0000X
3
X
2
X
1
X
0
)*
(X
7
X
6
X
5
X
4
X
3
X
2
X
1
X
0
)
* No need to resend the command again if it is set previously.
The read / write action to the Display Data RAM does not depend on the display mode. This means the
user can change the RAM content whether the target RAM content is being displayed or not.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SSD1852 | LCD Segment / Common Driver With Controller CMOS |
| SSD1852T2R1 | LCD Segment / Common Driver With Controller CMOS |
| SSD1852TR1 | LCD Segment / Common Driver With Controller CMOS |
| SSD1852Z | LCD Segment / Common Driver With Controller CMOS |
| SSD1854U | LCD Segment / Common Driver with Controller CMOS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SSD1828Z | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Segment / Common Driver with Controller CMOS |
| SSD1850 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS LCD Segment / Common Driver with Controller |
| SSD1850Z | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS LCD Segment / Common Driver with Controller |
| SSD1851 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS LCD Segment / Common Driver with Controller |
| SSD1851TR1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS LCD Segment / Common Driver with Controller |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。