- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄372239 > SRM20V512SLTT7 x8 SRAM PDF資料下載
參數(shù)資料
| 型號： | SRM20V512SLTT7 |
| 英文描述： | x8 SRAM |
| 中文描述： | x8的SRAM |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 85K |
| 代理商： | SRM20V512SLTT7 |
SRM20V512SLMT
7
5
I
FUNCTIONS
G
Truth Table
X : "H" or "L"
H
X
L
L
CS1
X
L
H
H
CS2
X
X
X
H
X
OE
X
L
H
WE
DATA I/O
I
DD
MODE
I
DDS,
I
DDS1
Hi
—
Z
Hi
—
Z
Input data
Hi
—
Z
Unselected
Unselected
Write
Output disable
I
DDS,
I
DDS1
I
DDA,
I
DDA1
L
H
L
H
Ouput data
Read
I
DDA,
I
DDA1
I
DDA,
I
DDA1
G
Reading data
Data is able to be read when the address is setted while holding CS1 = "L", CS2 = "H", OE = "L" and WE =
"H". Since Data I/O terminals are in high impedance state when OE = "H", the data bus line can be used for
any other objective, then access time apparently is able to be cut down.
G
Writing data
There are the following four ways of writing data into the memory.
(1) Hold CS2 = "H", WE = "L", set addresses and give "L" pulse to CS1.
(2) Hold CS1 = "L", WE = "L", set addresses and give "H" pulse to CS2.
(3) Hold CS1 = "L", CS2 = "H", set addresses and give "L" pulse to WE.
(4) After setting addresses, give "L" pulse to CS1, WE and give "H" pulse to CS2.
Anyway, data on the Data I/O terminals are latched up into the chip at the end of the period that CS1, WE are
"L" level, and CS2 is "H" level. As Data I/O terminals are in high impedance state when any of CS1, OE = "H",
or CS2 = "L", the contention on the data bus can be avoided.
G
Standby mode
When CS1 is "H" or CS2 is "L" level, the chip is in the standby mode which has retaning data operation. In this
case Data I/O terminals are Hi-Z, and all inputs of addresses, WE and data can be any "H" or "L". When CS1
and CS2 level are in the range over V
DD
-0.2V, or CS2 level is in the range under 0.2V, in the chip there is
almost no current flow except through the high resistance parts of the memory.
G
Data Retention at low Voltage Power Supply
During standby mode in which the data is retentive, the supply voltage
(
V
DD
)
can be in low voltage until V
DD
=
V
DDR
.
At this mode data reading and writing are impossible.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SRM2114C25 | x4 SRAM |
| SRM2114CL7 | x4 SRAM |
| SRM2114M25 | x4 SRAM |
| SRM2114ML7 | x4 SRAM |
| SRM2AL256LLM | x8 SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SRM20V512SLTX7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| SRM20V512SLYX7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| SRM2114C25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SRAM |
| SRM2114CL7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SRAM |
| SRM2114M25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。