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參數(shù)資料
| 型號： | SPT8000SIT |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 14-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQFP44 |
| 封裝： | PLASTIC, TQFP-44 |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 130K |
| 代理商： | SPT8000SIT |
6
10/12/01
SPT8000
Figure 1 – Timing Diagram
Data S1
Data S2
Data Out
D0D13
CLK
(VIN+) (VIN)
S1
tOD
S2
S3
tCLK
tCH
tCL
16 tCLK
FUNCTIONAL DESCRIPTION
The SPT8000 is a five-stage, pipeline analog-to-digital
converter (ADC) implemented in a fine-line CMOS pro-
cess. The block diagram on page one illustrates the
device’s functional block-level implementation. The input
sample-and-hold amplifier (SHA) guarantees its specified
performance for the input signal frequencies up to the
Nyquist frequency. It samples the differential analog input
signal at the rising edge of CLK input and holds it for the
next half-clock cycle. The SHA starts acquiring the input
signal once CLK input goes low and acquires the next
sample at the next rising edge of CLK.
Each of the first four pipeline stages consists of a flash
ADC (ADCn) and a multiplying digital-to-analog converter
(MDACn), where n=1, 2, 3 or 4. The first stage flash ADC
(ADC1) digitizes the output of the SHA and produces a
lower-resolution digital code corresponding to the SHA
output. The first stage MDAC1 subtracts from the SHA
output the ideal voltage corresponding to the ADC1 code
to generate the residue voltage, then amplifies the residue
and passes it to the second stage. The subsequent stages
2 through 4 repeat the same operation, and ADC5 gives
the last digital code corresponding to the output of
MDAC4. The digital codes from ADC1 to ADC5 are time
aligned and stored inside the “Data Alignment & Regis-
ters” block.
The SPT8000 incorporates one bit of overlap between two
subsequent pipeline stages and uses this redundancy to
digitally correct for errors in ADC1 through ADC4. In addi-
tion, the SPT8000 employs an internal digital calibration
circuitry to eliminate errors of the SHA and MDACs. Its
function is controlled by an internal microcontroller. When
in calibration mode, the SPT8000 configures itself such
that errors of each stage can be measured by the ADC
made of subsequent stages. The measured errors are
stored in on-chip digital memory (RAM). During subse-
quent normal conversions, the microcontroller looks up
the RAM contents and makes digital corrections of the er-
rors, to produce the final 14-bit digital output free of the
errors. The 14-bit digital output along with OTR (out-of-
range flag) are latched and buffered to drive the output
pins. These output buffers have their own power supply
and ground (OVDD and OGND), and can interface +5 V or
+3.3 V external logic circuitry.
The SPT8000 has an internal bandgap voltage reference
that produces a temperature-stable 1 V output at
VREF/EXTB pin. This voltage sets the input span of the
SPT8000 about CM of 2.25 V. Therefore, the input span
nominally is set to 1.25 V (VRC) to 3.25 V (VRT). Internal
buffers provide low-impedance outputs for CM, VRT and
VRC that are used throughout the pipeline stages. The out-
put impedance of the VREF/EXTB pin is set relatively high
(approximately 4.7 k
), allowing the user to override the
internal 1 V reference and change the input span.The user
can also drive VRT and VRC directly with external buffers.To
do this, VREF/EXTB must be shorted to AGND. Shorting
this pin to AGND disables the internal buffers driving VRT
and VRC.
INTERNAL DIGITAL CALIBRATION
The SPT8000 achieves the specified performance by in-
ternal digital calibration, eliminating the need for external
adjustments or trimming by the user.
The calibration takes advantage of the fact that the accu-
racy requirement for a pipeline stage is progressively
reduced. For example, the SHA and MDAC1 must be ac-
curate to 14 bits in order to achieve 14 bits of overall ADC
accuracy. If we assume that ADC1’s resolution is N and
that there is a one-bit overlap between the first and
second stages, the accuracy requirement for MDAC2 is
reduced to (14–N+1) bits (note: N>1). The obtainable
accuracy of a stage is set by the circuit’s non-idealities
such as device mismatches, finite bandwidth, finite gain,
etc. For the specific implementation of the SPT8000, the
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