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參數(shù)資料
| 型號： | SPT8000SIT |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 14-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQFP44 |
| 封裝： | PLASTIC, TQFP-44 |
| 文件頁數(shù)： | 6/11頁 |
| 文件大?。?/td> | 130K |
| 代理商： | SPT8000SIT |
4
10/12/01
SPT8000
DIFFERENTIAL LINEARITY ERROR (DLE) OR
DIFFERENTIAL NONLINEARITY (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differ-
ential Linearity Error is the maximum deviation, expressed
in LSBs, from this ideal value.
INTEGRAL LINEARITY ERROR (ILE) OR
INTEGRAL NONLINEARITY (INL)
The ideal transfer for an ADC is a straight line drawn
between “zero” and “full scale.” The point used as “zero”
occurs 0.5 LSB before the first code transition. “Full scale”
is defined as a level 1.5 LSB beyond the last code transi-
tion. ILE is the worst-case deviation of a code from the
straight line. The deviation of each code is measured from
the middle of that code.
MISSING CODE
A code with zero width is missing. A code that is missing
will have a DLE of –1. For example, as the input voltage is
increasing, the output will jump between the adjacent
codes, from 11...001 to 11...011, skipping 11...010. A
specification that guarantees no missing codes requires
that every code combination appear in a monotonically in-
creasing sequence as the analog input is increased.
OFFSET ERROR, BIPOLAR
In the differential mode, the major carry transition
(0111...1 to 1000...0) should occur for an analog value 0.5
LSB below mid scale (0 V differential input). The Offset
Error specifies the deviation of the actual transition from
that point.
GAIN ERROR
The last transition should occur at an analog value 1.5 LSB
below the nominal full scale. The first transition is 0.5 LSB
above the low end of the scale (–FS in bipolar converters).
The gain error is the deviation of the actual difference be-
tween the first and last code transitions from the ideal dif-
ference between the first and last transitions.
INPUT FULL-POWER BANDWIDTH
The frequency at which the amplitude of the recon-
structed fundamental signal is reduced by 3 dB for a full-
scale input.
CLOCK DUTY CYCLE
Ratio of clock pulse high (tCH) to total clock period (tCLK)
times 100%.
SPECIFICATION DEFINITIONS
Duty Cycle =
tCH
tCLK
X 100%
N =
SINAD – 1.76
6.02
SIGNAL-TO-NOISE RATIO (SNR)
The ratio of the power of the desired signal (fundamental)
to the sum of the power of noise signals at a given point in
time. The first 9 harmonics are excluded from the noise
signals. Usually expressed in dB.
HARMONIC
1.Of a sinusoidal wave, an integral multiple of the
frequency of the wave. Note: The frequency of the sine
wave is called the
fundamental frequency or the first
harmonic, the second harmonic is twice the fundamen-
tal frequency, the third harmonic is thrice the fundamen-
tal frequency, etc.
2.Of a periodic signal or other periodic phenomenon, such
as an electromagnetic wave or a sound wave, a compo-
nent frequency of the signal that is an integral multiple
of the fundamental frequency. Note: The fundamental
frequency is the reciprocal of the period of the periodic
phenomenon. Contrast with fundamental overtone.
TOTAL HARMONIC DISTORTION (THD)
The ratio of the sum of the power of first 9 harmonics
above the fundamental frequency to the power of the fun-
damental frequency. Usually expressed in dB.
SIGNAL-TO-NOISE AND DISTORTION RATIO
(SINAD)
The ratio of the power of the desired signal (fundamental)
to the sum of the power of all spectral components below
Nyquist Frequency, including noise and distortion. Usually
expressed in dB.
EFFECTIVE NUMBER OF BITS (ENOB)
SINAD = 6.02N + 1.76, where N is equal to the effective
number of bits.
SPURIOUS FREE DYNAMIC RANGE (SFDR)
The ratio of the fundamental sinusoidal power to the power
of the single largest harmonic or spurious signal.
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