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參數(shù)資料
| 型號： | SPC5200CBV466B |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 466 MHz, MICROPROCESSOR, PBGA272 |
| 封裝： | 27 X 27 MM, 1.27 MM PITCH, HALIDE FREE, PLASTIC, BGA-272 |
| 文件頁數(shù)： | 8/80頁 |
| 文件大?。?/td> | 788K |
| 代理商： | SPC5200CBV466B |
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MPC5200B Data Sheet, Rev. 0.6
Electrical and Thermal Characteristics
Freescale Semiconductor
16
3.3.3
Resets
The MPC5200B has three reset pins:
PORRESET - Power on Reset
HRESET - Hard Reset
SRESET - Software Reset
These signals are asynchronous I/O signals and can be asserted at any time. The input side uses a Schmitt
trigger and requires the same input characteristics as other MPC5200B inputs, as specified in the DC
Electrical Specifications section. Table 14 specifies the pulse widths of the Reset inputs.
NOTES:
1. For PORRESET the value of the minimum pulse width reflects the power on sequence. If PORRESET is asserted afterwards
its minimum pulse width equals the minimum given for HRESET related to the same reference clock.
2. The tVDD_stable describes the time which is needed to get all power supplies stable.
3. For tlock, refer to the Oscillator/PLL section of this specification for further details.
4. For tup_osc, refer to the Oscillator/PLL section of this specification for further details.
5. Following the deassertion of PORRESET, HRESET and SRESET remain low for 4096 reference clock cycles.
6. The deassertion of HRESET for at least the minimum pulse width forces the internal resets to be active for an additional 4096
clock cycles.
NOTE
As long as VDD is not stable the HRESET output is not stable.
tFALL
SYS_XTAL_IN fall time.
—
5.0
ns
A2.3
tDUTY
SYS_XTAL_IN duty cycle (measured at VM).
(2)
40.0
60.0
%
A2.4
CVIH
SYS_XTAL_IN input voltage high
2.0
—
V
A2.5
CVIL
SYS_XTAL_IN input voltage low
—
0.8
V
A2.6
NOTES:
1
CAUTION—The SYS_XTAL_IN frequency and system PLL_CFG[0-6] settings must be chosen such that the
resulting system frequencies do not exceed their respective maximum or minimum operating frequencies. See the
MPC5200B User Manual [1].
2
SYS_XTAL_IN duty cycle is measured at VM.
Table 14. Reset Pulse Width
Name
Description
Min Pulse Width
Max Pulse
Width
Reference Clock
SpecID
PORRESET
Power On Reset
tVDD_stable+tup_osc+tlock
—
SYS_XTAL_IN
A3.1
HRESET
Hardware Reset
4 clock cycles
—
SYS_XTAL_IN
A3.2
SRESET
Software Reset
4 clock cycles
—
SYS_XTAL_IN
A3.3
Table 13. SYS_XTAL_IN Timing (continued)
Sym
Description
Min
Max
Units
SpecID
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