參數(shù)資料
型號(hào): SPC5200CBV466B
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 466 MHz, MICROPROCESSOR, PBGA272
封裝: 27 X 27 MM, 1.27 MM PITCH, HALIDE FREE, PLASTIC, BGA-272
文件頁(yè)數(shù): 71/80頁(yè)
文件大?。?/td> 788K
代理商: SPC5200CBV466B
System Design Information
MPC5200B Data Sheet, Rev. 0.6
Freescale Semiconductor
73
For a board with a COP (common on-chip processor) connector, which accesses the JTAG interface and
which needs to reset the JTAG module, simply wiring JTAG_TRST and PORRESET is not recommended.
To reset the MPC5200B via the COP connector, the HRESET pin of the COP should be connected to the
HRESET pin of the MPC5200B. The circuitry shown in Figure 54 allows the COP to assert HRESET or
JTAG_TRST separately, while any other board sources can drive PORRESET.
7
JTAG_TCK
tck
100k Pull-Up
10k Pull-Up
O
6—
VDD(2)
——
5
See Note (3).
halted(3)
——
I
4JTAG_TRST
trst
100k Pull-Up
10k Pull-Up
O
3
JTAG_TDI
tdi
100k Pull-Up
10k Pull-Up
O
2
See Note (4).
qack(4)
——
O
1JTAG_TDO
tdo
I
NOTES:
1.
With respect to the emulator tool’s perspective:
Input is really an output from the embedded e300 core.
Output is really an input to the core.
2.
From the board under test, power sense for chip power.
3.
HALTED is not available from e300 core.
4.
Input to the e300 core to enable/disable soft-stop condition during breakpoints. MPC5200B
internally ties CORE_QACK to GND in its normal/functional mode (always asserted).
Table 53. COP/BDM Interface Signals (continued)
BDM
Pin #
MPC5200B
I/O Pin
BDM
Connector
Internal
Pull Up/Down
External
Pull Up/Down
I/O(1)
相關(guān)PDF資料
PDF描述
MPC5200CVR466B 32-BIT, 400 MHz, MICROPROCESSOR, PBGA272
MPC5200CVR466BR2 32-BIT, 400 MHz, MICROPROCESSOR, PBGA272
MPC5200VR400BR2 32-BIT, 400 MHz, MICROPROCESSOR, PBGA272
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