參數(shù)資料
型號(hào): SPC5200CBV466B
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 466 MHz, MICROPROCESSOR, PBGA272
封裝: 27 X 27 MM, 1.27 MM PITCH, HALIDE FREE, PLASTIC, BGA-272
文件頁數(shù): 14/80頁
文件大?。?/td> 788K
代理商: SPC5200CBV466B
Electrical and Thermal Characteristics
MPC5200B Data Sheet, Rev. 0.6
Freescale Semiconductor
21
Figure 6. Timing Diagram—Standard SDRAM Memory Write Timing
3.3.5.3
Memory Interface Timing-DDR SDRAM Read Command
The SDRAM Memory Controller uses a 1/4 period delayed MDQS strobe to capture the MDQ data. The
1/4 period delay value is calculated automatically by hardware.
Table 19. Standard SDRAM Write Timing
Sym
Description
Min
Max
Units
SpecID
tmem_clk
MEM_CLK period
7.5
ns
A5.8
tvalid
Control Signals, Address and MBA Valid
after rising edge of MEM_CLK
—tmem_clk*0.5+0.4
ns
A5.9
thold
Control Signals, Address and MBA Hold after
rising edge of MEM_CLK
tmem_clk*0.5
ns
A5.10
DMvalid
DQM valid after rising edge of MEM_CLK
tmem_clk*0.25+0.4
ns
A5.11
DMhold
DQM hold after rising edge of Mem_clk
tmem_clk*0.25-0.7
ns
A5.12
datavalid
MDQ valid after rising edge of MEM_CLK
tmem_clk*0.75+0.4
ns
A5.13
datahold
MDQ hold after rising edge of MEM_CLK
tmem_clk*0.75-0.7
ns
A5.14
MEM_CLK
Control Signals
MDQ (Data)
MA (Address)
NOTE: Control Signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN
Active
NOP
WRITE
NOP
thold
Row
Column
MBA (Bank Selects)
datahold
datavalid
tvalid
thold
tvalid
thold
tvalid
DQM (Data Mask)
DMvalid
DMhold
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