參數(shù)資料
型號(hào): SPC5200CBV400
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: MPC5200 Hardware Specifications
中文描述: 400 MHz, RISC PROCESSOR, PBGA272
封裝: 27 X 27 MM, 1.27 MM PITCH, PLASTIC, BGA-272
文件頁(yè)數(shù): 29/76頁(yè)
文件大小: 1404K
代理商: SPC5200CBV400
MOTOROLA
MPC5200 Hardware Specifications
29
Electrical and Thermal Characteristics
NOTES:
1.
2.
Wait states for Reads and Writes can be inserted when configured.
Dead cycles can be specified as 0 to 3. Dead cycles will be added to the end of Chip Select read access and will occur
in addition to any cycles which may already exist. These cycles provide a peripheral additional time to tri-state its bus
after a read operation. This is for all access types.
Transfer Size TSIZE(1:0) are available in Non-MUXed mode for MOST Graphics or Large Flash Modes only.
For understanding the different hold/valid/assertion/negation times refer to Figure 10.
The timing values in the above table are for a clock ratio of IP_CLK : PCI_CLK = 1 : 1 only.
The values will be different for other IP_CLK : PCI_CLK clock ratios.
3.
Figure 12 Timing Diagram - MUXed Mode
t
DH
DATA input to PCI CLK hold
-
1
ns
A7.28
Table 25 MUXed Mode Timing (continued)
Sym
Description
Min
Max
Units
Notes SpecID
PCI CLK
AD[24:0]
CSx
RW
ALE
AD[30:28]
AD[26:25]
AD[31,27]
Address[7:31]
Bank[0:1] bits
TSIZ[0:2] bits
ACK Input
Data or tri-state
Start Bus Tenure
End Bus Tenure
Data "tenure"
"Dack"
long
short
Address "tenure"
TS
long
short
tri-state
Wait States
(0-127)
(0-3)
Dead Cycles
Data or tri-state
Data or tri-state
Data or tri-state
tri-state
tri-state
tri-state
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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