參數(shù)資料
型號: SPC5200CBV400
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: MPC5200 Hardware Specifications
中文描述: 400 MHz, RISC PROCESSOR, PBGA272
封裝: 27 X 27 MM, 1.27 MM PITCH, PLASTIC, BGA-272
文件頁數(shù): 13/76頁
文件大?。?/td> 1404K
代理商: SPC5200CBV400
MOTOROLA
MPC5200 Hardware Specifications
13
Electrical and Thermal Characteristics
3.2.3 System PLL Electrical Characteristics
Table 10 System PLL Specifications
Characteristic
Symbol
Notes
Min
Typical
Max
Unit
SpecID
SYS_XTAL frequency
f
sys_xtal
1
1
The SYS_XTAL frequency and PLL Configuration bits must be chosen such that the resulting system frequency, CPU
(core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequen-
cies.
This represents total input jitter - short term and long term combined - and is guaranteed by design. Two different types
of jitter can exist on the input to core_sysclk, systemic and true random jitter. True random jitter is rejected, but the PLL.
Systemic jitter will be passed into and through the PLL to the internal clock circuitry, directly reducing the operating fre-
quency.
Relock time is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for
the PLL lock after a stable Vdd and core_sysclk are reached during the power-on reset sequence. This specification
also applies when the PLL has been disabled and subsequently re-enabled during sleep modes.
15.6
33.3
35.0
MHz
O3.1
SYS_XTAL cycle time
T
sys_xtal
1
66.6
30.0
28.5
ns
O3.2
SYS_XTAL clock input jitter
t
jitter
2
2
150
ps
O3.3
System VCO frequency
f
VCOsys
1
250
533
800
MHz
O3.4
System PLL relock time
t
lock
3
3
100
μ
s
O3.5
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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