參數(shù)資料
型號(hào): SPC5200CBV400
廠商: MOTOROLA INC
元件分類(lèi): 微控制器/微處理器
英文描述: MPC5200 Hardware Specifications
中文描述: 400 MHz, RISC PROCESSOR, PBGA272
封裝: 27 X 27 MM, 1.27 MM PITCH, PLASTIC, BGA-272
文件頁(yè)數(shù): 23/76頁(yè)
文件大小: 1404K
代理商: SPC5200CBV400
MOTOROLA
MPC5200 Hardware Specifications
23
Electrical and Thermal Characteristics
3.3.5.6
The SDRAM Memory Controller uses an internally skewed clock for reading DDR memory. The
programmable bits in the Reset Configuration Register used to account for unknown board delays are in
the CDM module. The internal read clock can be delayed up to 3 ns under worst operating conditions in 32
increments of 95 ps, (1.4 ns in 45 ps increments under best case operating conditions) by programming
the CDM Reset Configuration Register tap delay bits. Note: These bits in the CDM Reset Configuration
register are not ‘reset configured’ but have a hard coded reset value
and
are writable during operation.
Memory Interface Timing-DDR SDRAM Read Command
Figure 7 Timing Diagram—DDR SDRAM Memory Read Timing
Table 20 DDR SDRAM Memory Read Timing
Sym
Description
Min
Max
Units SpecID
t
mem_clk
MEM_CLK period
7.5
ns
A5.15
t
valid
Control Signals, Address and MBA
valid after rising edge of MEM_CLK
t
mem_clk
*0.5+0.4
ns
A5.16
t
hold
Control Signals, Address and MBA
hold after rising edge of MEM_CLK
t
mem_clk
*0.5
ns
A5.17
data
setup
Setup time skewed by CDM Reset
Config Reg [3:7] = 0b00010
0.4
ns
A5.18
data
hold
Hold time skewed by CDM Reset Con-
fig Reg [3:7] = 0b00010
2.34
ns
A5.19
MEM_CLK
Control Signals
MDQ (Data)
MA (Address)
MEM_CLK
MDQS (Data Strobe)
NOTE: Control Signals signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN
Active
NOP
READ
NOP
NOP
NOP
NOP
NOP
t
hold
Row
Column
MBA (Bank Selects)
data
hold
data
setup
t
valid
t
hold
t
valid
t
hold
t
valid
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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