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| 型號(hào)： | SPAKMC332GMPV16 |
| 廠(chǎng)商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 16 MHz, MICROCONTROLLER, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁(yè)數(shù)： | 82/265頁(yè) |
| 文件大?。?/td> | 6905K |
| 代理商： | SPAKMC332GMPV16 |
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STANDBY RAM WITH TPU EMULATION
MC68332
8-2
USER’S MANUAL
an address that overlaps the address of the module control register block. Writing a
valid base address to TRAMBAR[15:3] clears RAMDS and enables the array.
TRAMBAR can be written only once after a master reset. This prevents runaway soft-
ware from accidentally re-mapping the array. Because the locking mechanism is acti-
vated by the first write after a master reset, the base address field should be written in
a single word operation. Writing only one-half of the register prevents the other half
from being written. Note that in test mode the locking mechanism for TRAMBAR can
be disabled by the RTBA bit in the TRAMTST register.
8.4 TPURAM Privilege Level
The RASP field in TRAMMCR specifies whether access to the TPURAM module can
be made from the supervisor privilege level only or from either the user or supervisor
privilege level. If supervisor-only access is specified, an access from the user privilege
level is ignored by the TPURAM control logic and can be decoded externally. Refer to
for more information concerning privilege levels.
8.5 Normal Operation
In normal operation, TPURAM is accessed via the IMB by a bus master and is pow-
ered by VDD. The array can be accessed by byte, word, or long word. A byte or aligned
word access takes one bus cycle (two system clock cycles). A long word access re-
quires two bus cycles. Refer to SECTION 4 SYSTEM INTEGRATION MODULE for
more information concerning access times.
During normal operation, the TPU does not access the array and has no effect on the
operation of the TPURAM module.
8.6 Standby Operation
Standby mode maintains the RAM array when the MCU main power supply is turned
off. Low-power mode allows the central processing unit to control MCU power con-
sumption.
Relative voltage levels of the VDD and VSTBY pins determine whether the TPURAM
is in standby mode. TPURAM circuitry switches to the standby power source when
specified limits are exceeded. If specified standby supply voltage levels are main-
tained during the transition, there is no loss of memory when switching occurs. The
RAM array cannot be accessed while the TPURAM module is powered from VSTBY.
If standby operation is not desired, connect the VSTBY pin to the VSS pin.
ISB exceeds specified maximum standby current during the time VDD makes the tran-
sition from normal operating level to the level specified for standby operation. This oc-
curs within the voltage range VSB – 0.5 V ≥ VDD ≥ VSS + 0.5 V. Typically, ISB peaks
when VDD VSB – 1.5 V, and averages 1.0 mA over the transition period.
Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for standby switching and
power consumption specifications.
To prevent standby supply voltage from going below the specified minimum, a filter ca-
pacitor must be attached between the VSTBY and VSS pins. To calculate filter capac-
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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