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參數(shù)資料
| 型號(hào)： | SPAK56F807VF80 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 16-BIT, 80 MHz, OTHER DSP, PBGA160 |
| 封裝： | MOLD ARRAY PROCESS, BGA-160 |
| 文件頁數(shù)： | 4/48頁 |
| 文件大小： | 853K |
| 代理商： | SPAK56F807VF80 |
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12
DSP56F807 Preliminary Technical Data
MOTOROLA
2.8 Serial Peripheral Interface (SPI) Signals
6
PWMB0-5
Output
PWMB0-5— Six PWMB output pins.
3
ISB0-2
Input
ISB0-2— These three input current status pins are used for
top/bottom pulse width correction in complementary channel
operation for PWMB.
4
FAULTB0-3
Input
FAULTB0-3— These four Fault input pins are used for
disabling selected PWMB outputs in cases where fault
conditions originate off-chip.
Table 13. Serial Peripheral Interface (SPI) Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
MISO
GPIOE6
Input/
Output
Input/
Output
Input
SPI Master In/Slave Out (MISO)—This serial data pin is an input to
a master device and an output from a slave device. The MISO line
of a slave device is placed in the high-impedance state if the slave
device is not selected.
Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.
After reset, the default state is MISO.
1
MOSI
GPIOE5
Input/
Output
Input/
Output
Input
SPI Master Out/Slave In (MOSI)—This serial data pin is an output
from a master device and an input to a slave device. The master
device places data on the MOSI line a half-cycle before the clock
edge that the slave device uses to latch the data.
Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.
After reset, the default state is MOSI.
1
SCLK
GPIOE4
Input/
Output
Input/
Output
Input
SPI Serial Clock—In master mode, this pin serves as an output,
clocking slaved listeners. In slave mode, this pin serves as the data
clock input.
Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.
After reset, the default state is SCLK.
1
SS
GPIOE7
Input
Input/
Output
Input
SPI Slave Select—In master mode, this pin is used to arbitrate
multiple masters. In slave mode, this pin is used to select the slave.
Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.
After reset, the default state is SS.
Table 12. Pulse Width Modulator (PWMA and PWMB) Signals (Continued)
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
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