參數(shù)資料
型號(hào): SPAK56F807VF80
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號(hào)處理
英文描述: 16-BIT, 80 MHz, OTHER DSP, PBGA160
封裝: MOLD ARRAY PROCESS, BGA-160
文件頁數(shù): 29/48頁
文件大小: 853K
代理商: SPAK56F807VF80
Analog-to-Digital Converter (ADC) Characteristics
MOTOROLA
DSP56F807 Preliminary Technical Data
35
3.12 Analog-to-Digital Converter (ADC) Characteristics
Table 36. ADC Characteristics
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, VREF = VDD-0.3V, ADCDIV = 4, 9, or 14,
ADC clock = 4MHz, 3.0–3.6 V, TA = –40° to +85°C, CL 50 pF, fOP = 80 MHz
Characteristic
Symbol
Min
Typ
Max
Unit
Input voltages
VADIN
0
VDDA
1
1.
VDDA should be tied to the same potential as VDD via separate traces. VREF must be equal to or less than VDD and
must be greater than or equal to 2.7V.
V
Resolution
RES
12
12
Bits
Integral Non-Linearity2
2.
Measured in 10-90% range.
INL
+/- 2.5
+/- 4
LSB3
3.
LSB = Least Significant Bit.
Differential Non-Linearity
DNL
+/- 0.9
+/- 1
LSB3
Monotonicity
GUARANTEED
ADC internal clock
fADIC
0.5
5
MHz
Conversion range
RAD
VSSA
—VDDA
V
Conversion time
tADC
—6
tAIC cycles
4
Sample time
tADS
—1
tAIC cycles
4
Input capacitance
CADI
—5
pF4
Gain Error (transfer gain)
EGAIN
0.93
1.00
1.08
Total Harmonic Distortion
THD
60
64
Offset Voltage
VOFFSET
-90
-25
+10
mV
Signal-to-Noise plus Distortion
SINAD
55
60
Effective Number of Bits
ENOB
9
10
bit
Spurious Free Dynamic Range
SFDR
65
70
dB
ADC Quiescent Current (both ADCs)
IADC
39.3
mA
VREF Quiescent Current (both ADCs)
IVREF
11.85
14.5
mA
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