參數(shù)資料
型號(hào): SPAK56F807VF80
廠商: FREESCALE SEMICONDUCTOR INC
元件分類(lèi): 數(shù)字信號(hào)處理
英文描述: 16-BIT, 80 MHz, OTHER DSP, PBGA160
封裝: MOLD ARRAY PROCESS, BGA-160
文件頁(yè)數(shù): 19/48頁(yè)
文件大?。?/td> 853K
代理商: SPAK56F807VF80
26
DSP56F807 Preliminary Technical Data
MOTOROLA
3.6 External Bus Asynchronous Timing
Table 30. External Bus Asynchronous Timing1,2
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL 50 pF, fop = 80 MHz
1.
Timing is both wait state and frequency dependent. In the formulas listed, WS = the number of wait states and
T = Clock Period. For 80 MHz operation, T = 12.5ns.
2.
Parameters listed are guaranteed by design.
To calculate the required access time for an external memory for any frequency < 80 Mhz, use this formula:
Top = Clock period @ desired operating frequency
WS = Number of wait states
Memory Access Time = (Top*WS) + (Top- 11.5)
Characteristic
Symbol
Typical Min
Typical Max
Unit
Address Valid to WR Asserted
tAWR
6.5
—ns
WR Width Asserted
Wait states = 0
Wait states > 0
tWR
7.5
(T*WS)+7.5
ns
WR Asserted to D0–D15 Out Valid
tWRD
—T + 4.2
ns
Data Out Hold Time from WR Deasserted
tDOH
4.8
ns
Data Out Set Up Time to WR Deasserted
Wait states = 0
Wait states > 0
tDOS
2.2
(T*WS)+6.4
ns
RD Deasserted to Address Not Valid
tRDA
0—
ns
Address Valid to RD Deasserted
Wait states = 0
Wait states > 0
tARDD
18.7
(T*WS) + 18.7
ns
Input Data Hold to RD Deasserted
tDRD
0—
ns
RD Assertion Width
Wait states = 0
Wait states > 0
tRD
19
(T*WS)+19
ns
Address Valid to Input Data Valid
Wait states = 0
Wait states > 0
tAD
1
(T*WS)+1
ns
Address Valid to RD Asserted
tARDA
-4.4
ns
RD Asserted to Input Data Valid
Wait states = 0
Wait states > 0
tRDD
2.4
(T*WS) + 2.4
ns
WR Deasserted to RD Asserted
tWRRD
6.8
ns
RD Deasserted to RD Asserted
tRDRD
0—
ns
WR Deasserted to WR Asserted
tWRWR
14.1
ns
RD Deasserted to WR Asserted
tRDWR
12.8
ns
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