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參數(shù)資料
| 型號(hào)： | SNJ54LV125AFK |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS |
| 中文描述： | 翻兩番總線緩沖器門，三態(tài)輸出 |
| 文件頁數(shù)： | 4/17頁 |
| 文件大?。?/td> | 515K |
| 代理商： | SNJ54LV125AFK |
SCES124L DECEMBER 1997 REVISED APRIL 2005
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 5)
SN54LV125A
MIN
SN74LV125A
MIN
UNIT
MAX
MAX
VCC
Supply voltage
2
5.5
2
5.5
V
VCC = 2 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 2 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
1.5
1.5
VIH
High-level input voltage
VCC
×
0.7
VCC
×
0.7
VCC
×
0.7
VCC
×
0.7
VCC
×
0.7
VCC
×
0.7
V
0.5
0.5
VIL
Low-level input voltage
VCC
×
0.3
VCC
×
0.3
VCC
×
0.3
5.5
VCC
×
0.3
VCC
×
0.3
VCC
×
0.3
5.5
V
VI
Input voltage
0
0
V
VO
Output voltage
High or low state
0
VCC
5.5
0
VCC
5.5
V
3-state
0
0
VCC = 2 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 2 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
50
50
μ
A
IOH
High-level output current
2
2
8
8
mA
16
16
50
50
μ
A
IOL
Low-level output current
2
2
8
8
mA
16
16
200
200
t/
v
Input transition rise or fall rate
100
100
ns/V
20
20
TA
Operating free-air temperature
55
125
40
85
°
C
NOTE 5: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
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相關(guān)PDF資料 |
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|---|---|
| SN54LV125 | MINIATURE POWER RELAY |
| SN54LV125AFK | QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS |
| SN74LV125ANS | QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS |
| SN74LV125ADB | QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS |
| SN54LV125A | QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS |
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