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參數(shù)資料
| 型號： | SNJ54LV125AFK |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS |
| 中文描述： | 翻兩番總線緩沖器門，三態(tài)輸出 |
| 文件頁數(shù)： | 2/17頁 |
| 文件大?。?/td> | 515K |
| 代理商： | SNJ54LV125AFK |
SCES124L DECEMBER 1997 REVISED APRIL 2005
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
(each buffer)
INPUTS
OUTPUT
Y
OE
A
L
H
H
L
L
L
H
X
Z
logic diagram (positive logic)
2A
2Y
2OE
1A
1Y
1OE
1
2
4
5
3
6
4A
4Y
4OE
3A
3Y
3OE
10
9
13
12
8
11
Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, RGY, and W packages.
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| SN74LV125ADB | QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS |
| SN54LV125A | QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS |
相關代理商/技術參數(shù) |
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| SNJ54LVC00AFK | 制造商:Texas Instruments 功能描述: 制造商:Texas Instruments 功能描述:QUADRUPLE 2-INPUT POSITIVE-NAND GATE |
| SNJ54LVC00AJ | 制造商:Texas Instruments 功能描述:5962-9753301QCA, QUAD 2-IN POS-NAND GATE - Rail/Tube |
| SNJ54LVC00AW | 制造商:Texas Instruments 功能描述: |
| SNJ54LVC02AFK | 制造商:Texas Instruments 功能描述: |
| SNJ54LVC02AW | 制造商:Texas Instruments 功能描述:NOR Gate 4-Element 2-IN CMOS 14-Pin CFPAK Tube |
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