參數(shù)資料
型號(hào)： SN54LV125
廠商： Texas Instruments, Inc.
英文描述： MINIATURE POWER RELAY
中文描述： 翻兩番總線緩沖器門，三態(tài)輸出
文件頁數(shù)： 1/17頁
文件大?。?/td> 515K
代理商： SN54LV125
SCES124L DECEMBER 1997 REVISED APRIL 2005
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
2-V to 5.5-V V
CC
Operation
Max t
pd
of 6 ns at 5 V
Typical V
OLP
(Output Ground Bounce)
<0.8 V at V
CC
= 3.3 V, T
A
= 25
°
C
Typical V
OHV
(Output V
OH
Undershoot)
>2.3 V at V
CC
= 3.3 V, T
A
= 25
°
C
Support Mixed-Mode Voltage Operation on
All Ports
I
off
Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OE
1A
1Y
2OE
2A
2Y
GND
V
CC
4OE
4A
4Y
3OE
3A
3Y
SN54LV125A . . . J OR W PACKAGE
SN74LV125A . . . D, DB, DGV, N, NS,
OR PW PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
4A
NC
4Y
NC
3OE
1Y
NC
2OE
NC
2A
1
1
N
3
3
V
4
2
G
N
SN54LV125A . . . FK PACKAGE
(TOP VIEW)
NC No internal connection
SN74LV125A . . . RGY PACKAGE
(TOP VIEW)
1
14
7
8
2
3
4
5
6
13
12
11
10
9
4OE
4A
4Y
3OE
3A
1A
1Y
2OE
2A
2Y
1
3
V
G
description/ordering information
The ‘LV125A quadruple bus buffer gates are designed for 2-V to 5.5-V V
CC
operation.
These devices feature independent line drivers with 3-state outputs. Each output is disabled when the
associated output-enable (OE) input is high.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP N
Tube of 25
SN74LV125AN
SN74LV125AN
QFN RGY
Reel of 1000
SN74LV125ARGYR
LV125A
SOIC D
Tube of 50
SN74LV125AD
LV125A
Reel of 2500
SN74LV125ADR
40
°
C to 85
°
C
SOP NS
Reel of 2000
SN74LV125ANSR
74LV125A
SSOP DB
Reel of 2000
SN74LV125ADBR
LV125A
Tube of 90
SN74LV125APW
TSSOP PW
Reel of 2000
SN74LV125APWR
LV125A
Reel of 250
SN74LV125APWT
TVSOP DGV
Reel of 2000
SN74LV125ADGVR
LV125A
CDIP J
Tube of 25
SNJ54LV125AJ
SNJ54LV125AJ
55 C to 125 C
CFP W
LCCC FK
Tube of 150
Tube of 55
SNJ54LV125AW
SNJ54LV125AFK
SNJ54LV125AW
SNJ54LV125AFK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Copyright
2005, Texas Instruments Incorporated
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
相關(guān)PDF資料
PDF描述
SN54LV125AFK QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SN74LV125ANS QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SN74LV125ADB QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SN54LV125A QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SN74LV125ADGV IC LOGIC 541T OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS -40+85C SOIC-20 38/TUBE
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