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| 型號： | SN75LVDS83CZQLR |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 27/27頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FLATLINK TX 10-85MHZ 56BGA |
| 標準包裝： | 1,000 |
| 系列： | * |
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tsu
thold
Dn
CLKIN
SLLSE66A
– OCTOBER 2010 – REVISED SEPTEMBER 2011
SWITCHING CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
Delay time, CLKOUT
↑ after Yn valid
t0
(serial bit position 0, equal D1, D9,
-0.15
0
0.15
ns
D20, D5)
Delay time, CLKOUT
↑ after Yn valid
t1
(serial bit position 1, equal D0, D8,
1/
7 tc - 0.15
1/
7 tc + 0.15
ns
D19, D27)
Delay time, CLKOUT
↑ after Yn valid
t2
(serial bit position 2, equal D7, D18,
2/
7 tc - 0.15
2/
7 tc + 0.15
ns
D26. D23)
Delay time, CLKOUT
↑ after Yn valid
t3
(serial bit position 3; equal D6, D15,
3/
7 tc - 0.15
3/
7 tc + 0.15
ns
|Input clock jitter|
< 25ps (2)
D25, D17)
Delay time, CLKOUT
↑ after Yn valid
t4
(serial bit position 4, equal D4, D14,
4/
7 tc - 0.15
4/
7 tc + 0.15
ns
D24, D16)
Delay time, CLKOUT
↑ after Yn valid
t5
(serial bit position 5, equal D3, D13,
5/
7 tc - 0.15
5/
7 tc + 0.15
ns
D22, D11)
Delay time, CLKOUT
↑ after Yn valid
t6
(serial bit position 6, equal D2, D12,
6/
7 tc - 0.15
6/
7 tc + 0.15
ns
D21, D10)
tc(o)
Output clock period
tc
ns
tC = 13.3ns; clean reference clock, see
±26
Δtc(o)
Output clock cycle-to-cycle jitter (3)
ps
tC = 13.3ns with 0.05UI added noise
±44
modulated at 3MHz, see Figure 8
tw
High-level output clock pulse duration
4/
7 tc
ns
Differential output voltage transition
tr/f
See Figure 4
200
250
800
ps
time (tr or tf)
Enable time, SHTDN
↑ to phase lock
ten
15
s
(Yn valid)
Disable time, SHTDN
↓ to off-state
tdis
13
ns
(CLKOUT high-impedance)
(1)
All typical values are at VCC = 3.3 V, TA = 25°C.
(2)
|Input clock jitter| is the magnitude of the change in the input clock period.
(3)
The output clock cycle-to-cycle jitter is the largest recorded change in the output clock period from one cycle to the next cycle observed
over 15,000 cycles.Tektronix TDSJIT3 Jitter Analysis software was used to derive the maximum and minimum jitter value.
PARAMETER MEASUREMENT INFORMATION
All input timing is defined at IOVDD / 2 on an input signal with a 10% to 90% rise or fall time of less than 3 ns.
CLKSEL = 0V.
Figure 3. Set Up and Hold Time Definition
Copyright
2010–2011, Texas Instruments Incorporated
9
Product Folder Link(s): SN75LVDS83C
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| SN75LVDS83DGG | 功能描述:總線發(fā)射器 Flatlink RoHS:否 制造商:Texas Instruments 數(shù)據(jù)速率:135 Mpps 接口: 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSSOP-56 封裝:Reel |
| SN75LVDS83DGG | 制造商:Texas Instruments 功能描述:IC FLATLINK(TM) XMITTER 56-TSSOP 制造商:Texas Instruments 功能描述:IC, FLATLINK(TM) XMITTER 56-TSSOP 制造商:Texas Instruments 功能描述:IC, FLATLINK(TM) XMITTER 56-TSSOP; MSL:MSL 2 - 1 year; SVHC:No SVHC (19-Dec-2012); Base Number:75; Device Type:LVDS; No. of Pins:56; Operating Temperature Max:70C; Operating Temperature Min:0C; Operating Temperature Range:0C to ;RoHS Compliant: Yes |
| SN75LVDS83DGG | 制造商:Texas Instruments 功能描述:SEMICONDUCTOR |
| SN75LVDS83DGGG4 | 功能描述:總線發(fā)射器 Flatlink RoHS:否 制造商:Texas Instruments 數(shù)據(jù)速率:135 Mpps 接口: 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSSOP-56 封裝:Reel |
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