參數(shù)資料
型號: SN75LVDS83CZQLR
廠商: Texas Instruments
文件頁數(shù): 12/27頁
文件大小: 0K
描述: IC FLATLINK TX 10-85MHZ 56BGA
標準包裝: 1,000
系列: *
SLLSE66A
– OCTOBER 2010 – REVISED SEPTEMBER 2011
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
The SN75LVDS83C requires no external components and little or no control. The data bus appears the same at
the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The
only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge with a
low-level input, and the possible use of the Shutdown/Clear (SHTDN). SHTDN is an active-low input to inhibit the
clock, and shut off the LVDS output drivers for lower power consumption. A low-level on this signal clears all
internal registers to a low-level.
The SN75LVDS83C is characterized for operation over ambient air temperatures of -10
°C to 70°C.
ORDERING INFORMATION(1)
PART NUMBER
PART MARKING
PACKAGE
SN75LVDS83CZQLR
LVDS83C in BGA package
56-pin ZQL LARGE Tape and Reel
(1)
For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or
refer to our web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
(1)
VALUE
UNIT
MIN
MAX
Supply voltage range, VCC, IOVCC, LVDSVCC, PLLVCC(2)
-0.5
4
V
Voltage range at any output terminal
-0.5
VCC + 0.5
V
Voltage range at any input terminal
-0.5
IOVCC + 0.5
V
Continuous power dissipation
See the Thermal Information Table
Storage temperature, Ts
–65
150
°C
Human Body Model (HBM)(3) all pins
5
kV
ESD rating
Charged Device Model (CDM)(4) all pins
500
V
Machine Model (MM)(5) all pins
150
V
(1)
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2)
All voltages are with respect to the GND terminals.
(3)
In accordance with JEDEC Standard 22, Test Method A114-A.
(4)
In accordance with JEDEC Standard 22, Test Method C101.
(5)
In accordance with JEDEC Standard 22, Test Method A115-A.
2
Copyright
2010–2011, Texas Instruments Incorporated
Product Folder Link(s): SN75LVDS83C
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