參數(shù)資料
型號: SN75FC1000BPHD
廠商: Texas Instruments, Inc.
英文描述: Toggle Switch; Circuitry:DPDT; Switch Operation:On-On; Contact Current Max:12A; Actuator Style:Bat; Switch Terminals:Screw; Leaded Process Compatible:Yes RoHS Compliant: Yes
中文描述: 1千兆位光纖通道收發(fā)器
文件頁數(shù): 8/19頁
文件大小: 256K
代理商: SN75FC1000BPHD
SN75FC1000B
1-GIGABIT FIBRE CHANNEL TRANSCEIVER
SLLS371 – FEBRUARY 2000
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
comma character not on expected boundary
When synchronization is enabled and a K28.5 character straddles the expected 10-bit word boundary, then
word realignment is necessary. Realignment or shifting the 10-bit word boundary truncates the character
following the misaligned K28.5, but the following K28.5 and all subsequent data is aligned properly as shown
in Figure 2. The 10b specification requires that RCLK cycles can not be truncated and can only be stretched
or stalled in their current state during realignment. With this design the maximum stretch that occurs is an extra
10 bit times. This occurs during a worst case scenario when the K28.5 is aligned to the falling edge of RBC1
instead of the rising edge. Fibre channel compliant systems transmit a minimum of three consecutively ordered
K28.5 data sets between frames and ensure that the receiver sees at least two of K28.5 sets (the fabric is
allowed to drop one). Figure 2 shows the timing characteristics of the data realignment.
Systems that do not require framed data can disable byte alignment by tying SYNCEN low.
When a synchronization character is detected the SYNC signal is asserted high and is aligned with the K28.5
character. The duration of the SYNC-signal pulse is equal to the duration of the data which is half an RCLK
period.
RBC1
RBC0
SYNC
Serial Rx Data Stream
DIN_RxP – DIN_RxN
K28.5
Dxx.x
Dxx.x
Dxx.x
K28.5
Dxx.x
RD0 – RD9
K28.5
Dxx.x
Dxx.x
K28.5
Dxx.x
Dxx.x
K28.5
20 Bit Times
(MAX)
Typical Receive
Path Latency = 21 ns
Dxx.x
Dxx.x
Dxx.x
Worst Case
Misaligned K28.5
Corrupted Data
Misalignment
Corrected
10 Bit Times
10 Bit Times
Dxx.x
Dxx.x
K28.5
Dxx.x
Figure 2. Word Realignment Timing Characteristics Waveforms
data reception latency
The serial-to-parallel data latency is the time from when the first bit arrives at the receiver until it is output in the
aligned parallel word with RD0 received as first bit. The receive latency is typically 21 ns.
loop-back testing
The transceiver can provide a self-test function by enabling (LOOPEN to high level) the internal loop-back path.
Enabling LOOPEN causes serially transmitted data to be routed internally to the receiver. The parallel data
output can be compared to the parallel input data for functional verification. The external differential output is
held in a static state during loop-back testing.
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