參數(shù)資料
型號(hào): SN65HVD10QP
廠商: Texas Instruments, Inc.
英文描述: 3.3V RS 485 TRANSCEIVERS
中文描述: 3.3V的RS 485接口TRANSCEIVE恏巴
文件頁數(shù): 1/20頁
文件大小: 273K
代理商: SN65HVD10QP
SLLS505F FEBRUARY 2002 REVISED NOVEMBER 2003
FEATURES
Operates With a 3.3-V Supply
Bus-Pin ESD Protection Exceeds 16 kV HBM
1/8 Unit-Load Option Available (Up to 256
Nodes on the Bus)
Optional Driver Output Transition Times for
Signaling Rates
of 1 Mbps, 10 Mbps and
25 Mbps
Meets or Exceeds the Requirements of ANSI
TIA/EIA-485-A
Bus-Pin Short Circuit Protection From –7 V to
12 V
Low-Current Standby Mode
. . .
1
μ
A Typical
Open-Circuit, Idle-Bus, and Shorted-Bus
Failsafe Receiver
Thermal Shutdown Protection
Glitch-Free Power-Up and Power-Down
Protection for Hot-Plugging Applications
SN75176 Footprint
APPLICATIONS
Digital Motor Control
Utility Meters
Chassis-to-Chassis Interconnects
Electronic Security Stations
Industrial Process Control
Building Automation
Point-of-Sale (POS) Terminals and Networks
DESCRIPTION
The
SN75HVD11, SN65HVD12, and SN75HVD12 combine a
3-state differential line driver and differential input line
receiver that operate with a single 3.3-V power supply.
They are designed for balanced transmission lines and
meet or exceed ANSI standard TIA/EIA-485-A and ISO
8482:1993. These differential bus transceivers are
monolithic integrated circuits designed for bidirectional
data communication on multipoint bus-transmission lines.
The drivers and receivers have active-high and active-low
enables respectively, that can be externally connected
together to function as direction control. Very low device
standby supply current can be achieved by disabling the
driver and the receiver.
SN65HVD10,
SN75HVD10,
SN65HVD11,
The driver differential outputs and receiver differential
inputs connect internally to form a differential input/ output
(I/O) bus port that is designed to offer minimum loading to
the bus whenever the driver is disabled or V
CC
= 0. These
parts feature wide positive and negative common-mode
voltage ranges, making them suitable for party-line
applications.
1
2
3
4
8
7
6
5
R
RE
DE
D
V
CC
B
A
GND
D OR P PACKAGE
(TOP VIEW)
LOGIC DIAGRAM
(POSITIVE LOGIC)
1
2
3
4
6
7
A
B
R
RE
DE
D
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
www.ti.com
Copyright
20022003, Texas Instruments Incorporated
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