參數(shù)資料
型號： SN65HVD10QP
廠商： Texas Instruments, Inc.
英文描述： 3.3V RS 485 TRANSCEIVERS
中文描述： 3.3V的RS 485接口TRANSCEIVE恏巴
文件頁數(shù)： 6/20頁
文件大小： 273K
代理商： SN65HVD10QP
SLLS505F FEBRUARY 2002 REVISED NOVEMBER 2003
www.ti.com
6
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
12.5
TYP(1)
MAX
25
UNIT
tPLH
tPHL
Propagation delay time, low-to-high-level output
HVD10
20
ns
Propagation delay time, high-to-low-level output
HVD10
12.5
20
25
tPLH
Propagation delay time, low-to-high-level output
HVD11
HVD12
VID = 1.5 V to 1.5 V,
CL = 15 pF, See Figure 8
30
55
70
ns
tPHL
Propagation delay time, high-to-low-level output
HVD11
HVD12
30
55
70
ns
HVD10
1.5
tsk(p)
Pulse skew (|tPHL tPLH|)
HVD11
4
ns
HVD12
4
HVD10
8
Part-to-part skew
HVD11
15
ns
tsk(pp)(2)
HVD12
15
tr
tf
tPZH(1)
tPZL(1)
tPHZ
tPLZ
tPZH(2)
tPZL(2)
(1)All typical values are at 25
°
C and with a 3.3-V supply.
(2)tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate
with the same supply voltages, at the same temperature, and have identical packages and test circuits.
Output signal rise time
CL = 15 pF, See Figure 8
1
2
5
ns
Output signal fall time
1
2
5
Output enable time to high level
15
Output enable time to low level
CL = 15 pF, DE at 3 V,
See Figure 9
15
ns
Output disable time from high level
20
Output disable time from low level
15
Propagation delay time, standby-to-high-level output
CL = 15 pF
,
DE at 0,
See Figure 10
6
Propagation delay time, standby-to-low-level output
6
μ
s
THERMAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
121
MAX
UNITS
θ
JA
Junctiontoambient thermal resistance(2)
HighK board(3), No airflow
No airflow(4)
D pkg
°
C/W
P pkg
93
θ
JB
Junctiontoboard thermal resistance
HighK board
D pkg
67
°
C/W
°
C/W
See Note (4)
P pkg
57
θ
JC
Junctiontocase thermal resistance
D pkg
41
°
C/W
P pkg
55
RL= 60
, CL = 50 pF,
DE at VCC RE at 0 V,
Input to D a 50% duty cycle square
wave at indicated signaling rate
HVD10
(25 Mbps)
198
233
mW
PD
Device power dissipation
HVD11
(10 Mbps)
141
176
mW
HVD12
(500 kbps)
133
161
mW
TA
Ambient air temperature
HighK board, No airflow
No airflow(4)
D pkg
40
116
°
C
P pkg
40
123
TJSD
(1)See
Application Information
section for an explanation of these parameters.
(2)The intent of
θ
JA specification is solely for a thermal performance comparison of one package to another in a standardized environment. This
methodology is not meant to and will not predict the performance of a package in an application-specific environment.
(3)JSD517, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
(4)JESD5110, Test Boards for Through-Hole Perimeter Leaded Package Thermal Measurements.
Thermal shutdown junction temperature
165
°
C
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參數(shù)描述
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