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參數(shù)資料
| 型號(hào)： | SN74V3650-6PEU |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| 中文描述： | 的3.3V的CMOS先入先出存儲(chǔ)器 |
| 文件頁數(shù)： | 8/50頁 |
| 文件大?。?/td> | 729K |
| 代理商： | SN74V3650-6PEU |
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SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024
×
36, 2048
×
36, 4096
×
36, 8192
×
36, 16384
×
36, 32768
×
36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A
–
NOVEMBER 2001
–
REVISED MARCH 2003
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
partial reset (PRS)
A partial reset is accomplished when the PRS input is taken to a low state. As in the case of the master reset,
the internal read and write pointers are set to the first location of the RAM array, PAE goes low, PAF goes high,
and HF goes high.
Whichever mode is active at the time of partial reset remains selected (standard or FWFT mode). If standard
mode is active, FF goes high and EF goes low. If the FWFT mode is active, OR goes high and IR goes low.
Following partial reset, all values held in the offset registers remain unchanged. The programming method
(parallel or serial) active at the time of partial reset also is retained. The output register is initialized to all zeroes.
PRS is asynchronous.
A partial reset is useful for resetting the device during operation when reprogramming programmable-flag
offsets might not be convenient.
See Figure 6 for timing information.
retransmit (RT)
The retransmit operation allows previously read data to be accessed again. There are two modes of retransmit
operation: normal latency and zero latency. There are two stages to retransmit. The first stage is a setup
procedure that resets the read pointer to the first location of memory. The second stage is the actual retransmit,
which consists of reading out the memory contents, starting at the beginning of the memory.
Retransmit setup is initiated by holding RT low during a rising RCLK edge. REN and WEN must be high before
bringing RT low. When zero latency is utilized, REN need not be high before bringing RT low.
If standard mode is selected, the FIFO marks the beginning of the retransmit setup by setting EF low. The
change in level is noticeable only if EF was high before setup. During this period, the internal read pointer is
initialized to the first location of the RAM array.
When EF goes high, retransmit setup is complete and read operations can begin, starting with the first location
in memory. Because standard mode is selected, every word read, including the first word following retransmit
setup, requires a low on REN to enable the rising edge of RCLK.
See Figure 11 for timing information.
If FWFT mode is selected, the FIFO marks the beginning of the retransmit setup by setting OR high. During this
period, the internal read pointer is set to the first location of the RAM array.
When OR goes low, retransmit setup is complete. At the same time, the contents of the first location appear on
the outputs. Because FWFT mode is selected, the first word appears on the outputs and no low on REN is
necessary. Reading all subsequent words requires a low on REN to enable the rising edge of RCLK.
See Figure 12 for timing information.
In retransmit operation, zero-latency mode can be selected using the retransmit latency mode (RM) pin during
a master reset. This can be applied to the standard mode and the FWFT mode.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SN74V3660-10PEU | 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| SN74V3660-15PEU | 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| SN74V3670-10PEU | 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| SN74V3670-15PEU | 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| SN74V3690-15PEU | 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74V3650-7PEU | 功能描述:先進(jìn)先出 2048 x 36 Synch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74V3660-10PEU | 功能描述:先進(jìn)先出 4096 x 36 Synch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74V3660-15PEU | 功能描述:先進(jìn)先出 4096 x 36 Synch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74V3660-6PEU | 功能描述:先進(jìn)先出 4096 x 36 Synch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74V3660-7PEU | 功能描述:先進(jìn)先出 4096 x 36 Synch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
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