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參數(shù)資料
| 型號： | SN74V3650-10PEU |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| 中文描述： | 的3.3V的CMOS先入先出存儲器 |
| 文件頁數(shù)： | 9/50頁 |
| 文件大?。?/td> | 729K |
| 代理商： | SN74V3650-10PEU |
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SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024
×
36, 2048
×
36, 4096
×
36, 8192
×
36, 16384
×
36, 32768
×
36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A
–
NOVEMBER 2001
–
REVISED MARCH 2003
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
first-word fall-through/serial in (FWFT/SI)
FWFT/SI is a dual-purpose pin. During master reset, the state of the FWFT/SI input determines whether the
device operates in standard or FWFT mode.
If, at the time of master reset, FWFT/SI is low, standard mode is selected. This mode uses EF to indicate whether
any words are present in the FIFO memory. It also uses FF to indicate whether the FIFO memory has free space
for writing. In standard mode, every word read from the FIFO, including the first, must be requested using REN
and RCLK.
If, at the time of master reset, FWFT/SI is high, FWFT mode is selected. This mode uses OR to indicate whether
there is valid data at the data outputs (Qn). It also uses IR to indicate whether the FIFO memory has free space
for writing. In the FWFT mode, the first word written to an empty FIFO goes directly to Qn after three RCLK rising
edges, therefore, REN = low is not necessary. Subsequent words must be accessed using REN and RCLK.
After master reset, FWFT/SI acts as a serial input for loading PAE and PAF offsets into the programmable
registers. The serial input function can be used only when the serial loading method is selected during master
reset. Serial programming using the FWFT/SI pin functions the same way in both standard and FWFT modes.
write clock (WCLK)
A write cycle is initiated on the rising edge of the WCLK input. Data setup and hold times must be met, with
respect to the low-to-high transition of the WCLK. It is permissible to stop WCLK. Note that while WCLK is idle,
the FF/IR, PAF, and HF flags are not updated. WCLK is capable only of updating HF flag to low. The write and
read clocks can be independent or coincident.
write enable (WEN)
When WEN is low, data may be loaded into the FIFO RAM array on the rising edge of every WCLK cycle if the
device is not full. Data is stored in the RAM array sequentially and independently of any ongoing read operation.
When WEN is high, no new data is written in the RAM array on each WCLK cycle.
To prevent data overflow in the standard mode, FF goes low, inhibiting further write operations. After completion
of a valid read cycle, FF goes high, allowing a write to occur. FF is updated by two WCLK cycles + t
sk
after the
RCLK cycle.
To prevent data overflow in the FWFT mode, IR goes high, inhibiting further write operations. After completion
of a valid read cycle, IR goes low, allowing a write to occur. The IR flag is updated by two WCLK cycles + t
sk
after the valid RCLK cycle.
WEN is ignored when the FIFO is full in either FWFT or standard mode.
read clock (RCLK)
A read cycle is initiated on the rising edge of the RCLK input. Data can be read on the outputs, on the rising edge
of the RCLK input. It is permissible to stop RCLK. While RCLK is idle, the EF/OR, PAE, and HF flags are not
updated. RCLK is capable only of updating the HF flag to high. The write and read clocks can be independent
or coincident.
相關(guān)PDF資料 |
PDF描述 |
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| SN74V3650-15PEU | 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| SN74V3650-6PEU | 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| SN74V3660-10PEU | 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| SN74V3660-15PEU | 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| SN74V3670-10PEU | 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74V3650-15PEU | 功能描述:先進(jìn)先出 2048 x 36 Synch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74V3650-6PEU | 功能描述:先進(jìn)先出 2048 x 36 Synch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74V3650-7PEU | 功能描述:先進(jìn)先出 2048 x 36 Synch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74V3660-10PEU | 功能描述:先進(jìn)先出 4096 x 36 Synch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74V3660-15PEU | 功能描述:先進(jìn)先出 4096 x 36 Synch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
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