參數(shù)資料
型號: SN74LVTH182514DGG
廠商: Texas Instruments, Inc.
英文描述: 3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
中文描述: 的3.3V ABT生根粉掃描測試設備與20位通用總線收發(fā)器
文件頁數(shù): 1/34頁
文件大?。?/td> 548K
代理商: SN74LVTH182514DGG
SN54LVTH18514, SN54LVTH182514, SN74LVTH18514, SN74LVTH182514
3.3-V ABT SCAN TEST DEVICES
WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS670C – AUGUST 1996 – REVISED MARCH 1998
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Members of the Texas Instruments (TI
)
SCOPE
Family of Testability Products
Members of the TI Widebus
Family
State-of-the-Art 3.3-V ABT Design Supports
Mixed-Mode Signal Operation (5-V Input
and Output Voltages With 3.3-V V
CC
)
Support Unregulated Battery Operation
Down to 2.7 V
UBT
(Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
B-Port Outputs of
LVTH182514 Devices
Have Equivalent 25-
Series Resistors, So
No External Resistors Are Required
Compatible With the IEEE Std 1149.1-1990
(JTAG) Test Access Port and
Boundary-Scan Architecture
SCOPE
Instruction Set
– IEEE Std 1149.1-1990 Required
Instructions and Optional CLAMP and
HIGHZ
– Parallel-Signature Analysis at Inputs
– Pseudo-Random Pattern Generation
From Outputs
– Sample Inputs/Toggle Outputs
– Binary Count From Outputs
– Device Identification
– Even-Parity Opcodes
Package Options Include 64-Pin Plastic
Thin Shrink Small-Outline (DGG) and 64-Pin
Ceramic Dual Flat (HKC) Packages Using
0.5-mm Center-to-Center Spacings
description
The ’LVTH18514 and ’LVTH182514 scan test devices with 20-bit universal bus transceivers are members of
the TI SCOPE testability integrated-circuit family. This family of devices supports IEEE Std 1149.1-1990
boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is
accomplished via the 4-wire test access port (TAP) interface.
Additionally, these devices are designed specifically for low-voltage (3.3-V) V
CC
operation, but with the
capability to provide a TTL interface to a 5-V system environment.
Copyright
1998, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
parameters.
SCOPE, Widebus, UBT, and TI are trademarks of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54LVTH18514, SN54LVTH182514 . . . HKC PACKAGE
SN74LVTH18514, SN74LVTH182514 . . . DGG PACKAGE
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LEBA
OEBA
A1
A2
A3
GND
A4
A5
A6
V
CC
A7
A8
A9
GND
A10
A11
A12
A13
GND
A14
A15
A16
V
CC
A17
A18
A19
GND
A20
CLKENAB
CLKAB
TDO
TMS
CLKBA
CLKENBA
B1
B2
B3
GND
B4
B5
B6
V
CC
B7
B8
B9
GND
B10
B11
B12
B13
GND
B14
B15
B16
V
CC
B17
B18
B19
GND
B20
OEAB
LEAB
TDI
TCK
相關PDF資料
PDF描述
SN74LVTH18514DGG 3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SN54LVTH18514HKC 3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SN54LVTH182514HKC 3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SN74LVTH18512DGG Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 20pF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-1%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 1206; Termination: Sn60 Coated; Body Dimensions: 0.125" x 0.062" x 0.051"; Container: Bag; Features: MIL-PRF-55681: R Failure Rate
SN74LVTH182512DGG 3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
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