參數(shù)資料
型號: SN74HSTL16918DGG
廠商: Texas Instruments, Inc.
元件分類: 通用總線功能
英文描述: 9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH
中文描述: 9位到18位HSTL到LVTTL內(nèi)存地址鎖存
文件頁數(shù): 4/5頁
文件大?。?/td> 75K
代理商: SN74HSTL16918DGG
SN74HSTL16918
9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH
SCES096C – APRIL 1997 – REVISED JANUARY 1999
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
th
tsu
LOAD CIRCUIT
Data Input
VREF
1.25 V
0.25 V
VREF
VREF
1.25 V
0.25 V
1.25 V
0.25 V
VREF
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
VREF
VREF
1.25 V
0.25 V
VOH
VOL
Input
(see Note B)
Output
VREF
From Output
Under Test
CL = 80 pF
(see Note A)
500
LE
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr
1 ns, tf
1 ns.
C. The outputs are measured one at a time with one transition per measurement.
D. tPHL and tPLH are the same as tpd.
1.5 V
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
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