
SN74HSTL16918
9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH
SCES096C – APRIL 1997 – REVISED JANUARY 1999
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
1Q1
2Q1
1LE
D1
2LE
To Eight Other Channels
2
1
10
4
14
1D
C1
1D
C1
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
Input voltage range, V
I
(see Note 1)
Output voltage range, V
O
(see Note 1)
Input clamp current, I
IK
(V
I
< 0)
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 2)
Continuous output current, I
O
(V
O
= 0 to V
CC
)
Continuous current through each V
CC
or GND
Package thermal impedance,
θ
JA
(see Note 3)
Storage temperature range, T
stg
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51.
–0.5 V to 4.6 V
–0.5 V to V
CC
+ 0.5 V
–0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–50 mA
±
50 mA
±
50 mA
±
100 mA
89
°
C/W
–65
°
C to 150
°
C
recommended operating conditions (see Note 4)
MIN
NOM
MAX
UNIT
VCC
VREF
VI
VIH
VIL
VIH
VIL
IOH
IOL
TA
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs literature number SCBA004.
Supply voltage
3.15
3.45
V
Reference voltage
0.68
0.75
0.9
V
Input voltage
0
1.5
V
AC high-level input voltage
All inputs
VREF+200 mV
V
AC low-level input voltage
All inputs
VREF–200 mV
V
DC high-level input voltage
All inputs
VREF+100 mV
V
DC low-level input voltage
All inputs
VREF–100 mV
–24
V
High-level output current
mA
Low-level output current
24
mA
°
C
Operating free-air temperature
0
70