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參數(shù)資料
| 型號(hào)： | SN74GTLPH16612DGG |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER |
| 中文描述： | 18位LVTTL至GTLP通用總線收發(fā)器 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 166K |
| 代理商： | SN74GTLPH16612DGG |
SN74GTLPH16612
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES326 – MARCH 2000
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
functional description
Data flow in each direction is controlled by the clock-enables (CEAB and CEBA), latch-enables (LEAB and
LEBA), clock (CLKAB and CLKBA), and output-enables (OEAB and OEBA).
For A-to-B data flow, when CEAB is low, the device operates on the low-to-high transition of CLKAB for the
flip-flop and on the high-to-low transition of LEAB for the latch path, i.e., if CEAB and LEAB are low, the A data
is latched, regardless of the state of CLKAB (high or low) and if LEAB is high, the device is in transparent mode.
When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state.
The data flow for B to A is similar to A to B, except that CEBA, OEBA, LEBA, and CLKBA are used.
FUNCTION TABLE
INPUTS
OUTPUT
B
MODE
CEAB
OEAB
LEAB
CLKAB
A
X
H
X
X
X
Z
Isolation
L
L
L
H or L
X
B0
B0§
L
Latched storage of A data
L
L
L
H or L
X
X
L
H
X
L
Transparent
X
L
H
X
↑
↑
X
H
H
L
L
L
L
L
Clocked storage of A data
L
L
L
H
H
H
L
L
X
B0§
Clock inhibit
A-to-B data flow is shown. B-to-A data flow is similar, but uses OEBA, LEBA, CLKBA,
and CEBA.
Output level before the indicated steady-state input conditions were established, provided
that CLKAB was high before LEAB went low.
§Output level before the indicated steady-state input conditions were established.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| SN74GTLPH16612DL | 功能描述:轉(zhuǎn)換 - 電壓電平 18B LVTTL To GTLP Uni Bus Transceiver RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTLPH16612DLR | 功能描述:轉(zhuǎn)換 - 電壓電平 18B LVTTL To GTLP Uni Bus Transceiver RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTLPH16612GR | 功能描述:轉(zhuǎn)換 - 電壓電平 18B LVTTL To GTLP Uni Bus Transceiver RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTLPH16912GR | 功能描述:轉(zhuǎn)換 - 電壓電平 18-Bit LVTTL-to-GTLP Univ Bus Transceiver RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTLPH16912VR | 功能描述:總線收發(fā)器 18-Bit LVTTL-to-GTLP Univ Bus Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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