- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄365653 > SN74GTLPH16612DGG (Texas Instruments, Inc.) 18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER PDF資料下載
參數(shù)資料
| 型號(hào)： | SN74GTLPH16612DGG |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER |
| 中文描述： | 18位LVTTL至GTLP通用總線收發(fā)器 |
| 文件頁(yè)數(shù)： | 2/11頁(yè) |
| 文件大?。?/td> | 166K |
| 代理商： | SN74GTLPH16612DGG |
SN74GTLPH16612
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES326 – MARCH 2000
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
Figure 1 shows actual device output waveforms using a synchronous clock at 75 MHz. The test backplane is
a 16-slot, 14-inch board with loaded impedance of 33
.
V
TT
is 1.5 V, V
REF
is 1 V, and R
TT
pullup resistor is 50
.
The driver is in slot 8, with receivers in alternate slots 1, 3, 5, 7, 10, 12, 14, and 16. Receiver slot 1 signals are
shown. The signal becomes progressively worse as the receiver moves closer to the driver or the spacing
between receiver cards is reduced. The clock is independent of the data and the system clock frequency is
limited by the backplane flight time to about 80 MHz to 90 MHz. This frequency can be increased even more
(30% to 40%) if the clock is generated and transmitted together with the data from the driver card (source
synchronous).
The SN74GTLPH16612 is a medium-drive (34 mA), 18-bit universal bus transceiver, containing D-type latches
and D-type flip-flops to allow data flow in transparent, latched, clocked, and clock-enabled modes. This UBT
can replace any of the functions shown in Table 1.
Table 1. SN74GTLPH16612 UBT Replacement Functions
FUNCTION
8 BIT
9 BIT
10 BIT
16 BIT
18 BIT
Transceiver
’245, ’623, ’645
’863
’861
’16245, ’16623
’16863
Buffer/driver
’241, ’244, ’541
’827
’16241, ’16244, ’16541
’16825
Latched transceiver
’543
’16543
’16472
Latch
’373, ’573
’843
’841
’16373
’16843
Registered transceiver
’646, ’652
’16646, ’16652
’16474
Flip-flop
’374, ’574
’821
’16374
Standard UBT
’16500, ’16501
Universal bus driver
’16835
Registered transceiver with CLK enable
’2952
’16470, ’16952
Flip-flop with CLK enable
’377
’823
’16823
Standard UBT with CLK enable
’16600, ’16601
SN74GTLPH16612 UBT replaces all above functions
GTLP is a TI derivative of the Gunning transceiver logic (GTL) JEDEC standard JESD 8-3. The ac specification
of the SN74GTLPH16612 is given only at the preferred higher noise-margin GTLP, but this device can be used
at either GTL (V
TT
= 1.2 V and V
REF
= 0.8 V) or GTLP (V
TT
= 1.5 V and V
REF
= 1 V) signal levels.
The B port normally operates at GTLP levels, while the A-port and control inputs are compatible with LVTTL
logic levels and are 5-V tolerant. V
REF
is the reference input voltage for the B port.
To improve signal integrity, the SN74GTLPH16612 B-port output transition time is optimized for distributed
backplane loads.
V
CC
(5 V) supplies the internal and GTLP circuitry, while V
CC
(3.3 V) supplies the LVTTL output buffers.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven LVTTL inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not recommended.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74GTLPH16612 is characterized for operation from –40
°
C to 85
°
C.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SN74GTLPH16912VR | CAP |
| SN74H60 | DUAL 4-INPUT EXPANDERS |
| SN54H60 | DUAL 4-INPUT EXPANDERS |
| SN74H60J | DUAL 4-INPUT EXPANDERS |
| SN74H60N | DUAL 4-INPUT EXPANDERS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74GTLPH16612DL | 功能描述:轉(zhuǎn)換 - 電壓電平 18B LVTTL To GTLP Uni Bus Transceiver RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTLPH16612DLR | 功能描述:轉(zhuǎn)換 - 電壓電平 18B LVTTL To GTLP Uni Bus Transceiver RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTLPH16612GR | 功能描述:轉(zhuǎn)換 - 電壓電平 18B LVTTL To GTLP Uni Bus Transceiver RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTLPH16912GR | 功能描述:轉(zhuǎn)換 - 電壓電平 18-Bit LVTTL-to-GTLP Univ Bus Transceiver RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTLPH16912VR | 功能描述:總線收發(fā)器 18-Bit LVTTL-to-GTLP Univ Bus Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。