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參數(shù)資料
| 型號： | SN74GTLP1394DGV |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 2-BIT LVTTL-TO-GTL ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SELECTABLE POLARITY |
| 中文描述： | 2位LVTTL對天然氣制油可調(diào)EDGE的速率總線收發(fā)器具有可選的極性 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 143K |
| 代理商： | SN74GTLP1394DGV |
SN74GTLP1394
2-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
WITH SELECTABLE POLARITY
SCES286 – OCTOBER 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Bidirectional Interface Between GTL+
Signal Levels and LVTTL Logic Levels
LVTTL Interfaces Are 5-V Tolerant
High-Drive GTL+ Outputs (100 mA)
LVTTL Outputs (–24 mA/24 mA)
Variable Edge-Rate Control (ERC) Input
Selects GTL+ Rise and Fall Times for
Optimal Data-Transfer Rate and Signal
Integrity
I
off
, Power-Up 3-State, and BIAS V
CC
Support Live Insertion
Polarity Control Selects True or
Complementary Outputs
Package Options Include Plastic
Small-Outline (D), Thin Very Small-Outline
(DGV), and Thin Shrink Small-Outline (PW)
Packages
description
The SN74GTLP1394 is a high-drive 2-bit 3-wire bus transceiver that provides LVTTL-to-GTL+ and
GTL+-to-LVTTL signal-level translation. It allows for transparent and inverted transparent modes of data
transfer with separate LVTTL input and LVTTL output pins. The device provides a high-speed interface between
cards operating at LVTTL logic levels and a backplane operating at GTL+ signal levels and is especially
designed to work with the Texas Instruments TSB14C01A 1394 Backplane Physical-Layer Controller.
High-speed (about two times faster than standard LVTTL or TTL) backplane operation is a direct result of
GTLP’s reduced output swing (<1 V), reduced input threshold levels, improved differential input, and output
edge control (OEC
). Improved GTLP OEC circuits minimize bus settling time and have been designed and
tested using several backplane models. The high drive is suitable for driving double-terminated low-impedance
backplanes using incident-wave switching.
GTL+ is the Texas Instruments derivative of the Gunning transceiver logic (GTL) JEDEC standard JESD 8-3.
The AC specification of the SN74GTLP1394 is given only at the preferred higher noise margin GTL+, but the
user has the flexibility of using this device at either GTL (V
TT
= 1.2 V and V
REF
= 0.8 V) or GTL+ (V
TT
= 1.5 V
and V
REF
= 1 V) signal levels.
Normally, the B port operates at GTL or GTL+ levels. The A inputs, Y outputs, and control inputs are compatible
with LVTTL logic levels and are 5-V tolerant. V
REF
is the reference input voltage for the B port.
This device is fully specified for live-insertion applications using I
off
, power-up 3-state, and BIAS V
CC
. The I
off
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power
down, which prevents driver conflict. The BIAS V
CC
circuitry precharges and preconditions the B-port
input/output connections, preventing disturbance of active data on the backplane during card insertion or
removal, and permits true live-insertion capability.
High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC
input voltage between GND and V
CC
adjusts the B-port output rise and fall times.
This allows the designer to
optimize system data-transfer rate and signal integrity to the backplane load.
P
Copyright
1999, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
D, DGV, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OEBY
Y1
Y2
V
CC
A1
A2
OEAB
ERC
BIAS V
CC
GND
B1
GND
B2
GND
V
REF
T/C
OEC is a trademark of Texas Instruments Incorporated.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74GTLP1394DGVR | 功能描述:轉(zhuǎn)換 - 電壓電平 2bit Bus RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTLP1394DR | 功能描述:轉(zhuǎn)換 - 電壓電平 2bit Bus RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTLP1394DRE4 | 功能描述:轉(zhuǎn)換 - 電壓電平 2-Bit LVTTL/GTLP Bus Xcvr Adj-Edge-Rate RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTLP1394DRG4 | 功能描述:轉(zhuǎn)換 - 電壓電平 2B LVTTL to GTLP Adj Edg RateBus Xcvr RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTLP1394PW | 功能描述:轉(zhuǎn)換 - 電壓電平 2-Bit LVTTL/GTLP Bus Xcvr Adj-Edge-Rate RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
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