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參數(shù)資料
| 型號(hào)： | SN74GTLP1394RGYR |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY |
| 中文描述： | 2位LVTTL至GTLP可調(diào)EDGE的速率總線收發(fā)器配劈開LVTTL港口，反饋路徑，和可選的極性 |
| 文件頁數(shù)： | 1/25頁 |
| 文件大?。?/td> | 737K |
| 代理商： | SN74GTLP1394RGYR |
www.ti.com
FEATURES
TI-OPC Circuitry Limits Ringing on
Unevenly Loaded Backplanes
OEC Circuitry Improves Signal Integrity and
Reduces Electromagnetic Interference
Bidirectional Interface Between GTLP Signal
Levels and LVTTL Logic Levels
Split LVTTL Port Provides a Feedback Path
for Control and Diagnostics Monitoring
LVTTL Interfaces Are 5-V Tolerant
High-Drive GTLP Outputs (100 mA)
LVTTL Outputs (–24 mA/24 mA)
Variable Edge-Rate Control (ERC) Input
Selects GTLP Rise and Fall Times for Optimal
D, DGV, OR PW PACKAGE
(TOP VIEW)
RGY PACKAGE
(TOP VIEW)
1
16
8
9
2
3
4
5
6
7
15
14
13
12
11
10
GND
B1
GND
B2
GND
V
REF
Y1
Y2
V
CC
A1
A2
OEAB
O
T
B
E
C
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OEBY
Y1
Y2
V
CC
A1
A2
OEAB
ERC
BIAS V
CC
GND
B1
GND
B2
GND
V
REF
T/C
DESCRIPTION/ORDERING INFORMATION
SN74GTLP1394
2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES286F–OCTOBER 1999–REVISED APRIL 2005
Data-Transfer Rate and Signal Integrity in
Distributed Loads
I
off
, Power-Up 3-State, and BIAS V
CC
Support
Live Insertion
Polarity Control Selects True or
Complementary Outputs
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER
SN74GTLP1394RGYR
SN74GTLP1394D
SN74GTLP1394DR
SN74GTLP1394PWR
SN74GTLP1394DGVR
TOP-SIDE MARKING
GP1394
QFN – RGY
Tape and reel
Tube
Tape and reel
Tape and reel
Tape and reel
SOIC – D
GTLP1394
–40°C to 85°C
TSSOP – PW
TVSOP – DGV
GP394
GP394
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TI-OPC, OEC, TI are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright 1999–2005, Texas Instruments Incorporated
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74GTLP1395DGVR | 功能描述:轉(zhuǎn)換 - 電壓電平 Dual 1bit LVTTL-GTLP RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTLP1395DW | 功能描述:轉(zhuǎn)換 - 電壓電平 2 1-Bit LVTTL/GTLP Bus Xcvr Adj-Eg-Rate RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTLP1395DWE4 | 功能描述:轉(zhuǎn)換 - 電壓電平 2 1-Bit LVTTL/GTLP Bus Xcvr Adj-Eg-Rate RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTLP1395DWG4 | 功能描述:轉(zhuǎn)換 - 電壓電平 Two 1B LVTTL GTLP Adj Edg RateBus Xcvr RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTLP1395DWR | 功能描述:轉(zhuǎn)換 - 電壓電平 Dual 1bit LVTTL-GTLP RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
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