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參數(shù)資料
| 型號(hào)： | SN74GTLP1395GQNR |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | Low-Voltage High-Speed Quadruple Differential Line Driver 16-SOIC 0 to 70 |
| 中文描述： | 兩個(gè)1位LVTTL至GTLP可調(diào)EDGE的速率總線收發(fā)器與劈開LVTTL港口，反饋路徑，和可選的極性 |
| 文件頁數(shù)： | 1/21頁 |
| 文件大小： | 443K |
| 代理商： | SN74GTLP1395GQNR |
SN74GTLP1395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT FEEDBACK PATH, AND SELECTABLE POLARITY
SCES349C – JUNE 2001 – REVISED NOVEMBER 2001
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
TI-OPC
Circuitry Limits Ringing on
Unevenly Loaded Backplanes
OEC
Circuitry Improves Signal Integrity
and Reduces Electromagnetic Interference
Bidirectional Interface Between GTLP
Signal Levels and LVTTL Logic Levels
Split LVTTL Port Provides a Feedback Path
for Control and Diagnostics Monitoring
LVTTL Interfaces Are 5-V Tolerant
High-Drive GTLP Outputs (100 mA)
LVTTL Outputs (–24 mA/24 mA)
Variable Edge-Rate Control (ERC) Input
Selects GTLP Rise and Fall Times for
Optimal Data-Transfer Rate and Signal
Integrity in Distributed Loads
I
off
, Power-Up 3-State, and BIAS V
CC
Support Live Insertion
Polarity Control Selects True or
Complementary Outputs
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description
The SN74GTLP1395 is two 1-bit, high-drive, 3-wire bus transceivers that provide LVTTL-to-GTLP and
GTLP-to-LVTTL signal-level translation for applications, such as primary and secondary clocks, that require
individual output-enable and true/complement controls. The device allows for transparent and inverted
transparent modes of data transfer with separate LVTTL input and LVTTL output pins, which provide a feedback
path for control and diagnostics monitoring. The device provides a high-speed interface between cards
operating at LVTTL logic levels and a backplane operating at GTLP signal levels and is designed especially to
work with the Texas Instruments 3.3-V 1394 backplane physical-layer controller. High-speed (about three times
faster than standard LVTTL or TTL) backplane operation is a direct result of GTLP reduced output swing (<1 V),
reduced input threshold levels, improved differential input, OEC
circuitry, and TI-OPC
circuitry. Improved
GTLP OEC and TI-OPC circuitry minimizes bus settling time, and have been designed and tested using several
backplane models. The high drive allows incident-wave switching in heavily loaded backplanes, with equivalent
load impedance down to 11
.
GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3.
The ac specification of the SN74GTLP1395 is given only at the preferred higher noise margin GTLP, but the
user has the flexibility of using this device at either GTL (V
TT
= 1.2 V and V
REF
= 0.8 V) or GTLP (V
TT
= 1.5 V
and V
REF
= 1 V) signal levels. For information on using GTLP devices in FB+/BTL applications, refer to TI
application reports,
Texas Instruments GTLP Frequently Asked Questions
,
literature number SCEA019, and
GTLP in BTL Applications
, literature number SCEA017.
Copyright
2001, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DGV, DW, OR PW PACKAGE
(TOP VIEW)
1Y
1T/C
2Y
GND
1OEAB
V
CC
1A
GND
2A
2OEAB
1OEBY
2T/C
2OEBY
GND
1B
ERC
2B
GND
V
REF
BIAS V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OEC and TI-OPC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74GTLP1395PW | 功能描述:轉(zhuǎn)換 - 電壓電平 2 1-Bit LVTTL/GTLP Bus Xcvr Adj-Eg-Rate RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTLP1395PWE4 | 功能描述:轉(zhuǎn)換 - 電壓電平 2 1-Bit LVTTL/GTLP Bus Xcvr Adj-Eg-Rate RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTLP1395PWG4 | 功能描述:轉(zhuǎn)換 - 電壓電平 Two 1B LVTTL GTLP Adj Edg RateBus Xcvr RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTLP1395PWR | 功能描述:轉(zhuǎn)換 - 電壓電平 2 1-Bit LVTTL/GTLP Bus Xcvr Adj-Eg-Rate RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTLP1395PWRE4 | 功能描述:轉(zhuǎn)換 - 電壓電平 Quad Bus Buffer Gate With 3-State Outputs RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
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