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參數(shù)資料
| 型號(hào)： | SN74BCT8374ANT |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SCAN TEST DEVICES WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS |
| 中文描述： | 掃描測(cè)試設(shè)備與八路D型邊沿觸發(fā)觸發(fā)器 |
| 文件頁(yè)數(shù)： | 13/26頁(yè) |
| 文件大?。?/td> | 474K |
| 代理商： | SN74BCT8374ANT |
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SN54BCT8374A, SN74BCT8374A
SCAN TEST DEVICES
WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
SCBS045E – JUNE 1990 – REVISED JULY 1996
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
parallel-signature analysis (PSA)
Data appearing at the device input terminals is compressed into a 16-bit parallel signature in the shift-register
elements of the BSCs on each rising edge of TCK. This data is then updated in the shadow latches of the input
BSCs and applied to the inputs of the normal on-chip logic. Data in the shadow latches of the output BSCs
remains constant and is applied to the device outputs. Figure 6 shows the 16-bit linear-feedback shift-register
algorithm through which the signature is generated. An initial seed value should be scanned into the BSR before
performing this operation.
=
1D
1Q
2D
3D
4D
5D
6D
7D
8D
2Q
3Q
4Q
5Q
6Q
7Q
8Q
=
Figure 6. 16-Bit PSA Configuration
simultaneous PSA and PRPG (PSA/PRPG)
Data appearing at the device input terminals is compressed into an 8-bit parallel signature in the shift-register
elements of the input BSCs on each rising edge of TCK. This data is then updated in the shadow latches of the
input BSCs and applied to the inputs of the normal on-chip logic. At the same time, an 8-bit pseudo-random
pattern is generated in the shift-register elements of the output BSCs on each rising edge of TCK, updated in
the shadow latches, and applied to the device output terminals on each falling edge of TCK. Figure 7 shows
the 8-bit linear-feedback shift-register algorithm through which the signature and patterns are generated. An
initial seed value should be scanned into the BSR before performing this operation. A seed value of all zeroes
will not produce additional patterns.
=
1D
1Q
2D
3D
4D
5D
6D
7D
8D
2Q
3Q
4Q
5Q
6Q
7Q
8Q
=
Figure 7. 8-Bit PSA/PRPG Configuration
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74BCT8374ANTE4 | 功能描述:特定功能邏輯 Device w/Octal D-Typ Edge-Trig Flip-Flop RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SN74BCT8374NT | 制造商:Texas Instruments 功能描述:Flip Flop, Octal, D Type, 24 Pin, Plastic, DIP |
| SN74BCT899DW | 制造商:Texas Instruments 功能描述: |
| SN74CB373384DBQR | 制造商:Texas Instruments 功能描述: |
| SN74CB3Q16210DGGR | 功能描述:數(shù)字總線開(kāi)關(guān) IC Fixed LDO Volt Reg RoHS:否 制造商:Texas Instruments 開(kāi)關(guān)數(shù)量:24 傳播延遲時(shí)間:0.25 ns 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TSSOP-56 封裝:Reel |
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