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參數(shù)資料
| 型號： | SN74BCT8240ADWR |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SCAN TEST DEVICES WITH OCTAL INVERTING BUFFERS |
| 中文描述： | 掃描測試設備與八進制反向緩沖器 |
| 文件頁數(shù)： | 12/26頁 |
| 文件大?。?/td> | 473K |
| 代理商： | SN74BCT8240ADWR |
SN54BCT8240A, SN74BCT8240A
SCAN TEST DEVICES
WITH OCTAL INVERTING BUFFERS
SCBS067E – FEBRUARY 1990 – REVISED DECEMBER 1996
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
boundary-control-register opcode description
The BCR opcodes are decoded from BCR bits 1–0, as shown in Table 3. The selected test operation is
performed while the RUNT instruction is executed in the Run-Test/Idle state. The following descriptions detail
the operation of each BCR instruction and illustrate the associated PSA and PRPG algorithms.
Table 3. Boundary-Control Register Opcodes
BINARY CODE
BIT 1
→
BIT 0
MSB
→
LSB
00
DESCRIPTION
Sample inputs/toggle outputs (TOPSIP)
01
Pseudo-random pattern generation/16-bit mode (PRPG)
10
Parallel-signature analysis/16-bit mode (PSA)
11
Simultaneous PSA and PRPG/8-bit mode (PSA/PRPG)
It should be noted, in general, that while the control input BSCs (bits 17–16) are not included in the sample,
toggle, PSA, or PRPG algorithms, the output-enable BSCs (bits 17–16 of the BSR) do control the drive state
(active or high impedance) of the selected device output terminals.
sample inputs/toggle outputs (TOPSIP)
Data appearing at the device input terminals is captured in the shift-register elements of the input BSCs on each
rising edge of TCK. This data is then updated in the shadow latches of the input BSCs and applied to the inputs
of the normal on-chip logic. Data in the shift-register elements of the output BSCs is toggled on each rising edge
of TCK, updated in the shadow latches, and applied to the device output terminals on each falling edge of TCK.
pseudo-random pattern generation (PRPG)
A pseudo-random pattern is generated in the shift-register elements of the BSCs on each rising edge of TCK
and then updated in the shadow latches and applied to the device output terminals on each falling edge of TCK.
This data also is updated in the shadow latches of the input BSCs and applied to the inputs of the normal on-chip
logic. Figure 5 shows the 16-bit linear-feedback shift-register algorithm through which the patterns are
generated. An initial seed value should be scanned into the BSR before performing this operation. A seed value
of all zeroes will not produce additional patterns.
=
1A1
1Y1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
Figure 5. 16-Bit PRPG Configuration
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SN74BCT8240ADWRE4 | 功能描述:特定功能邏輯 Prog PCM w/Microphn Amps & Speaker Drvr RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SN74BCT8240ADWRG4 | 功能描述:特定功能邏輯 IEEE Std 1149.1 Bndry Sacn Tst Devic RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SN74BCT8240ANT | 功能描述:緩沖器和線路驅(qū)動器 Device w/Octal Inverting Buffers RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| SN74BCT8240ANTE4 | 功能描述:特定功能邏輯 Device w/Octal Inverting Buffers RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SN74BCT8244ADW | 功能描述:特定功能邏輯 Device w/Octal Buffers RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
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